Shared Systag Identifier Caching to Reduce Command Backlogs

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Solution Overview

Problem

Traditional memory sub-systems face increased latency and processing inefficiencies due to individual processing cores operating independently, leading to backlog when handling access commands, as each core processes commands without aiding others experiencing backlog.

Innovation Solution

Implementing an internal command system that generates and shares systags across multiple frontend processing cores, allowing them to collaboratively perform access operations, reducing latency and increasing overall processing capabilities by dynamically allocating tasks among cores.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If individual processing cores operate independently to handle access commands, then each core can process commands autonomously, but latency increases and command backlog occurs when multiple cores experience backlog simultaneously

Engineering Contradiction:
Improvecommand processing throughputVSAvoidaccess command latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

Multiple frontend processing cores are merged into a unified system that shares a common systag (system tag) structure. This allows the cores to collaborate on command processing by sharing backlog information and coordinating access operations, transforming independent core operation into a coordinated team effort that reduces overall latency and prevents command backlog.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system implements feedback mechanisms where processing cores monitor and report their backlog status through shared systags. This feedback loop enables cores to detect when others are experiencing backlog and adjust their behavior accordingly, allowing the system to dynamically balance workload and prevent individual cores from becoming bottlenecks.

Inventive Principle:
Principle #23Feedback

2Ease of manufacture

If each processing core processes access commands independently, then implementation is simple, but processing efficiency decreases due to lack of collaboration

Engineering Contradiction:
Improveimplementation simplicityVSAvoidprocessing efficiency
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The systag structure serves multiple functions simultaneously: it identifies commands, tracks backlog status, enables core coordination, and facilitates efficient resource allocation. This multi-functionality is achieved through a unified data structure that can be interpreted by any frontend processing core, maintaining implementation simplicity while dramatically improving processing efficiency through collaboration.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If processing cores operate in isolation, then system complexity is low, but overall performance is limited by individual core capabilities

Engineering Contradiction:
Improvecore operation structureVSAvoidoverall system performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The systag acts as an intermediary mechanism between processing cores, enabling them to communicate and coordinate their operations. This intermediary structure introduces minimal complexity to the individual cores while enabling powerful collaborative behavior at the system level, thereby improving overall reliability and performance without significantly increasing the complexity of individual core operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250335271A1Caching identifiers for access commands
Publication Date: 2025.10.30 MICRON TECHNOLOGY INC
  • US20250335271A1 patent drawing
  • US20250335271A1 patent drawing
  • US20250335271A1 patent drawing

AI summary

Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.