Differential Input Stage Using Shared-Tail NMOS Pairs
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Solution Overview
Problem
Existing amplifier input stages that use both n-type metal oxide semiconductor (NMOS) and p-type metal oxide semiconductor (PMOS) transistors suffer from high power consumption, complex circuit design, and large surface area due to the need for separate tail currents and additional circuitry to combine their outputs, limiting their efficiency and cost-effectiveness.
Innovation Solution
A differential input stage comprising a pair of standard NMOS transistors and a pair of natural NMOS transistors, which operate together to handle input signals across a wide range without the need for PMOS transistors, reducing power consumption, circuit complexity, and size by sharing a single tail current and eliminating the requirement for separate cascaded current sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If both NMOS and PMOS transistors are used in the input stage, then the input stage can handle a wide input range, but power consumption increases and circuit complexity increases
Solution Approach 1:
The patent combines both NMOS and PMOS transistors into a single differential pair sharing common tail current sources, merging previously separate circuit blocks into one integrated structure that handles wide input ranges while reducing power consumption and complexity
Solution Approach 2:
The differential input stage is designed to universally handle both high and low input voltage ranges using the same transistor pair, eliminating the need for separate NMOS-only and PMOS-only stages and their associated tail currents
2Adaptability or versatility
If both NMOS and PMOS transistors are used in the input stage, then the input stage can handle a wide input range, but the circuit design becomes more complex
Solution Approach 1:
The patent merges separate NMOS and PMOS differential pairs with their respective tail currents into a single unified differential input stage, reducing the number of independent circuit blocks and simplifying the overall design while maintaining wide input range capability
Solution Approach 2:
The patent extracts and eliminates the need for separate tail current sources for NMOS and PMOS transistors, removing redundant circuit elements and simplifying the biasing network while preserving the wide input voltage range functionality
3Adaptability or versatility
If both NMOS and PMOS transistors are used in the input stage, then the input stage can handle a wide input range, but the surface area increases
Solution Approach 1:
The patent merges previously separate NMOS and PMOS transistor pairs into a single compact differential structure, reducing the total transistor count and eliminating duplicate tail current source circuitry, thereby decreasing the overall layout area
4Reliability
If separate tail currents are used for NMOS and PMOS transistors, then each transistor type can operate independently, but power consumption increases and circuit complexity increases
Solution Approach 1:
The patent combines separate tail current sources into a shared common tail current that serves both NMOS and PMOS transistors, reducing the total number of current sources and their associated biasing circuits while maintaining proper operation across wide input ranges
Solution Approach 2:
The common tail current source is designed to universally bias both NMOS and PMOS transistors simultaneously, allowing a single circuit element to perform the function previously requiring two separate elements, thereby reducing power consumption and complexity
Data Source
AI summary
In some embodiments, a differential input stage comprises a first n-type metal oxide semiconductor transistor (NMOS) pair coupled to a first input and a second input, a second NMOS pair coupled to the first input, a first output node, the second input, and a second output node, a first diode coupled to the first NMOS pair and the first output node, a second diode coupled to the first NMOS pair and the second output node, and a cascaded current source coupled to the first NMOS pair and the second NMOS pair.