Shared-Terminal FeFET Memory Cell Structure for Lower IR Drop
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Solution Overview
Problem
Traditional NAND-type memory using ferroelectric field effect transistors (FeFETs) faces issues with small read margin due to high variability in ferroelectric material grain/domains and high IR drop, leading to low read/program speed.
Innovation Solution
The implementation of a memory device with a ferroelectric field effect transistor (FeFET) and a second transistor sharing gate, source, and drain terminals, along with a ferroelectric capacitor, enhances current flow and access speed by enlarging the current through memory cells, thereby improving read and write speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional NAND-type memory using FeFETs is used, then the device structure is simple, but the read margin is small due to high variability from ferroelectric material grain/domains
Solution Approach 1:
The memory cell is divided into two separate transistors (first transistor and second transistor) instead of using a single FeFET. This segmentation allows the ferroelectric capacitor to be shared between the two transistors' gate terminals, reducing the impact of ferroelectric material variability on the overall read margin while maintaining a relatively simple device structure.
2Device complexity
If traditional FeFET-based NAND memory is used, then the device configuration is compact, but the IR drop is very high causing low read/program speed
Solution Approach 1:
By segmenting the memory cell into two transistors with shared terminals, the current flow path is optimized. The shared gate, source, and drain terminals between the first and second transistors create a configuration that reduces IR drop while maintaining compact device configuration.
Solution Approach 2:
The first transistor and second transistor share common gate terminal, source terminal, and drain terminal, along with the ferroelectric capacitor. This merging of terminals consolidates the current path and reduces resistance, thereby reducing IR drop and improving read/program speed while keeping the device configuration compact.
3Productivity
If a dual-transistor configuration with shared terminals is implemented, then current flow and access speed improve, but the device complexity increases
Solution Approach 1:
The dual-transistor configuration achieves high access speed by merging the gate, source, and drain terminals between the first and second transistors, as well as sharing the ferroelectric capacitor. This merging approach increases productivity through improved current flow while minimizing the increase in device complexity by reusing common terminals and components.
Data Source
AI summary
A method includes providing a substrate including a channel region, the substrate comprising a two-stage structure having a first surface, a second surface higher than the first surface and a third surface connected between the first surface and the second surface; covering the substrate from a top thereof with an oxide layer; forming a ferroelectric material strip on a topmost surface of the oxide layer; and forming a gate strip covering the ferroelectric material strip and the oxide layer from a top of the gate strip.