Shared Timer ESD Protection Circuit for Compact Semiconductor Pads
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Solution Overview
Problem
The challenge in semiconductor devices is to reduce the size of ESD protection circuits while maintaining effective protection from static electricity, particularly in the context of shrinking chip sizes and the need to arrange protection circuits near power supply and input/output pads without compromising electrical characteristics.
Innovation Solution
The solution involves sharing a timer circuit between two ESD protection circuits, allowing for the omission of the timer in one circuit and reducing its size, while maintaining the number of protection circuits, thus enabling their placement near power supply and input/output pads without increasing pad pitch, and utilizing shared noise filter and buffer circuits to enhance electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of ESD protection circuits is reduced to match shrinking chip sizes, then chip size is reduced, but the ability to maintain effective electrical characteristics and protection performance deteriorates
Solution Approach 1:
The patent merges the timer circuit functionality into the voltage detection circuit, creating a integrated protection circuit that combines timing control and voltage detection functions. This integration reduces the total circuit area while maintaining the necessary protection performance, directly addressing the contradiction between size reduction and reliability maintenance.
Solution Approach 2:
The voltage detection circuit is designed to perform multiple functions: it detects voltage thresholds and also implements timing control previously handled by a separate timer circuit. This multi-functionality allows the circuit to maintain full protection capabilities while occupying less area, resolving the contradiction between compact size and effective protection.
2Adaptability or versatility
If ESD protection circuits are placed near power supply and input/output pads to reduce pad pitch, then device integration is improved, but circuit size must be minimized to avoid increasing pad pitch
Solution Approach 1:
By merging the timer circuit into the voltage detection circuit, the overall protection circuit size is reduced, enabling placement near power supply and I/O pads without increasing pad pitch, thus improving device integration while maintaining adaptability.
Solution Approach 2:
The patent optimizes the circuit layout by arranging components in a compact configuration that utilizes available space efficiently, allowing the protection circuit to be positioned close to pads without occupying excessive area, thereby improving spatial utilization and device integration.
3Reliability
If shared noise filter and buffer circuits are used to enhance electrical characteristics, then protection effectiveness is improved, but circuit complexity increases
Solution Approach 1:
The patent combines multiple protection functions including voltage detection, timing control, noise filtering, and buffering into a single integrated circuit structure. This merging approach enhances electrical characteristics through shared high-quality subcircuits while actually reducing overall complexity compared to having separate circuits for each function.
Solution Approach 2:
The integrated protection circuit uses shared noise filter and buffer circuits that serve multiple functions simultaneously, improving electrical characteristics for all protection functions while avoiding the complexity of duplicating these circuits for each function separately.
Data Source
AI summary
A semiconductor device includes first and second protection circuits. The first protection circuit includes a timer circuit, a voltage detection circuit, and a discharge element. The second protection circuit includes a discharge circuit. The timer circuit is connected between a first pad on a power supply potential side and a second pad on a reference potential side. The voltage detection circuit is connected between the first and second pads on an output side of the timer circuit. The discharge element is connected between the first and second pads on an output side of the voltage detection circuit. The discharge circuit is connected between a third pad on the power supply potential side and a fourth pad on the reference potential side on the output side of the timer circuit.