Shared Timer Interface Circuit for Reducing Surplus Counters
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Solution Overview
Problem
Existing timer devices with surplus counters due to fewer timers being used by external devices result in increased circuit scale.
Innovation Solution
An interface circuit with a first storage circuit, a second circuit performing counter operations, and a control circuit that enables selective enable/disable of timer operations based on external device inputs, reducing the number of active timers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a timer device includes a plurality of timers and a plurality of counters that are respectively associated with the plurality of timers, then the timer device can provide multiple timer functions, but when the number of timers used by the external device is smaller than the number of timers provided in the timer device, one or some timers are not used by the external device, which increases the circuit scale due to surplus counters
Solution Approach 1:
The patent makes a single counter circuit capable of serving multiple timer functions by controlling its operation through different clock signals and control signals. The counter circuit can be selectively enabled or disabled based on which timer is being used, allowing one counter to replace multiple dedicated counters while maintaining the ability to provide multiple timer functions.
Solution Approach 2:
The patent introduces dynamic control mechanisms where the counter circuit's operational state (enabled or disabled) changes based on the selected timer. The control circuit dynamically adjusts the counter's participation in timer operations according to the active timer selection, optimizing resource utilization and reducing the need for static, dedicated counter circuits for each timer.
2Reliability
If the timer device provides multiple timers with dedicated counters, then each timer has its own counting resources, but this results in surplus counters when fewer timers are used, increasing the circuit scale
Solution Approach 1:
The patent merges multiple dedicated counter circuits into a single shared counter circuit that can be selectively activated. By combining the counting resources and using multiplexing techniques with control signals, the patent achieves the same functional reliability with fewer physical components, reducing circuit scale while maintaining timer operation independence through selective enabling.
3Adaptability or versatility
If the circuit includes all possible timer and counter components, then the device can support all timer configurations, but the circuit scale increases due to unused components
Solution Approach 1:
The patent implements a universal counter circuit design that can adapt to different timer configurations through control signals and clock selection. Instead of providing separate counter circuits for each timer configuration, a single versatile counter circuit performs all necessary counting functions by receiving different clock inputs and control signals, thereby supporting multiple timer configurations with a reduced number of components.
Solution Approach 2:
The patent changes the operational parameters of the counter circuit (such as clock frequency, enable/disable state, and reset conditions) based on the selected timer configuration. By dynamically adjusting these parameters through control signals, the same counter hardware can adapt to different timer requirements without requiring additional components, thus maintaining adaptability while reducing component quantity.
Data Source
AI summary
An interface circuit includes a first storage circuit that holds first timer selection information indicating which of a plurality of timers is to be selected; a second circuit including a first circuit that performs a counter operation, and a register update signal generation circuit that outputs, based on an output of the first circuit, a first register update signal for updating a register, the second circuit being capable of operating as any one of the plurality of timers; and a control circuit that controls, based on the first timer selection information from the first storage circuit and counter identification information that is received from an external device and that indicates any one of a plurality of counters associated with the plurality of timers, whether to enable or disable write to the first circuit or read from the first circuit.