Shared Timing Graph Propagation for Multi-Mode Static Timing Analysis
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Solution Overview
Problem
Current approaches to performing timing analyses for integrated circuits across multiple constraint modes and delay corners require separate runs for each view, leading to increased runtime and memory consumption, and often result in quality of results (QoR) degradation and performance issues.
Innovation Solution
The technique involves performing a single timing analysis run for multiple views, maintaining relevant timing information independently for each view while avoiding the simplistic union analysis of conventional methods, ensuring that each view is analyzed similarly to separate runs, thereby achieving the same quality of results as individual runs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate runs are performed for each timing analysis view, then the quality of results is maintained, but the runtime and memory consumption increase
Solution Approach 1:
The patent segments the timing analysis process by maintaining separate timing information structures for each view while sharing common circuit topology. Each view's timing data is independently tracked and propagated, allowing parallel processing of multiple views without interference, thus reducing total runtime while preserving individual view accuracy
Solution Approach 2:
The patent creates a universal timing analysis framework that handles multiple views simultaneously through a single run. The system is designed to process different constraint modes and delay corners in one execution, eliminating the need for separate runs while maintaining the quality of results for each view through independent timing information maintenance
2Measurement precision
If separate runs are performed for each timing analysis view, then the quality of results is maintained, but the memory consumption increases
Solution Approach 1:
The patent segments memory usage by allocating timing information structures specifically for each view while sharing common circuit data. This segmentation allows efficient memory utilization where only view-specific timing data is duplicated, reducing overall memory consumption compared to running separate analyses while maintaining result quality
Solution Approach 2:
The patent merges multiple view analyses into a single runtime environment by combining shared circuit topology with view-specific timing information. This merging approach reduces redundant memory allocation that would occur in separate runs, as common data structures are instantiated once and shared across all views
3Productivity
If a single timing analysis run is performed for multiple views, then runtime and memory consumption are reduced, but the quality of results may degrade
Solution Approach 1:
The patent applies local quality by maintaining view-specific timing information with appropriate precision for each constraint mode and delay corner. Each view's timing data is independently propagated and analyzed with the same rigor as separate runs, ensuring local accuracy is preserved even within a unified multi-view analysis framework
Solution Approach 2:
The patent segments the timing analysis computation to preserve view independence within a single run. By separately tracking and propagating timing information for each view through the circuit topology, the system ensures that each view receives dedicated analysis resources and produces results equivalent to individual separate runs
Data Source
AI summary
According to certain aspects, the present embodiments include techniques for performing a single timing analysis run for a plurality of views representing different modes and/or corners. An embodiment analyzes and maintains relevant timing information that is different for different views, but otherwise maintains the same information for all views. This allows each individual view in a single run to be analyzed in the same manner as separate runs for each separate view, thereby ensuring the same QoR. These and other embodiments provide substantial savings in runtime and memory consumption over other approaches.