Shared Timing Control Circuit for Multi-Target Signal Scheduling
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Solution Overview
Problem
Existing microcomputers face challenges in performing versatile timing control due to the need for multiple timers, leading to increased circuit size and limitations in handling diverse control targets with varying counter combinations.
Innovation Solution
A timing control device with a storage unit for timing control information, selectors for outputting data based on identification information, a comparator for generating coincidence signals, and an output control unit for generating timing signals, allowing for versatile timing control by selectively switching between multiple timing control information sets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple timers are used for controlling multiple control targets, then timing control capability is improved, but circuit size increases
Solution Approach 1:
The patent implements a single timer that can be shared across multiple control targets through time-division multiplexing. The timer is alternately allocated to different control targets in a cyclic manner, allowing one timer to perform the functions that would traditionally require multiple dedicated timers. This universal approach maintains timing control capability while reducing the number of timer circuits needed.
Solution Approach 2:
The patent introduces dynamic allocation of the timer resource to different control targets based on timing requirements. The system dynamically switches the timer's assignment between control targets according to a predetermined cycle, enabling flexible timing control for multiple targets without requiring static dedicated timer circuits for each target.
2Adaptability or versatility
If multiple coincidence detection units are used for multiple timing signals, then timing signal generation capability is improved, but circuit size increases
Solution Approach 1:
The patent employs a single coincidence detection unit that is shared across multiple timing signal generation tasks. The coincidence detection unit is time-division multiplexed to detect coincidences for different control targets sequentially, enabling the generation of multiple timing signals without requiring multiple dedicated coincidence detection units. This reduces circuit complexity while maintaining the capability to generate multiple timing signals.
Solution Approach 2:
The patent merges the functionality of multiple coincidence detection units into a single unified unit. By combining the detection functions and sharing the unit across different control targets through time-division multiplexing, the system achieves the same timing signal generation capability with reduced hardware complexity.
3Measurement precision
If timer values are transferred to coincidence detection at every timing control, then timing precision is improved, but CPU interrupt frequency increases
Solution Approach 1:
The patent implements periodic transfer of timer values to the coincidence detection unit according to a predetermined cycle, rather than transferring at every timing control event. This periodic approach maintains timing precision by ensuring regular synchronization while significantly reducing the frequency of CPU interrupts compared to continuous transfer schemes.
Solution Approach 2:
The system maintains continuous timing control functionality by using a buffer to store timer values between periodic transfers. The coincidence detection unit operates continuously using the buffered values, ensuring uninterrupted timing signal generation while the CPU only needs to update the buffer periodically, thus maintaining productivity while preserving timing precision.
Data Source
AI summary
Provided is a timing control device including: a storage unit that stores multiple pieces of timing control information including identification information and expected value data; a first selector that selectively outputs any of the multiple pieces of timing control information; a second selector that selectively outputs any of data items output from data output devices based on the identification information; a reference data generation unit that generates reference data based on expected value data and a data item output from the second selector in synchronization with a switching of the timing control information; a comparator that compares the reference data with the data item output from the second selector and outputs a coincidence signal when the reference data and the data item coincide with each other; and an output control unit that outputs a timing signal according to the coincidence signal.