Shared TLB Selective Flushing for Multi-Processor Latency

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Java execution remains slow due to latency induced by native tasks such as real-time processing and garbage collection, hindering wider acceptance in the marketplace.

Innovation Solution

A multi-processor system with a Java Stack Machine (JSM) and a RISC-Based Main Processor Unit (MPU), where the operating system runs exclusively on the MPU, and a middle layer software distributes tasks between processors, utilizing a shared translation lookaside buffer (TLB) with task identifiers for selective flushing and synchronization logic to manage processor operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a shared TLB is used between multiple processors, then memory translation efficiency is improved, but selective flushing capability is lost

Engineering Contradiction:
Improvememory translation efficiencyVSAvoidselective flushing capability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The TLB is segmented by introducing processor-specific identifiers (such as CPU ID bits) into the TLB entry structure. This allows the shared TLB to be logically divided into processor-specific portions, enabling selective flushing of entries associated with particular processors while maintaining the shared physical structure and overall translation efficiency.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the operating system runs on multiple processors, then system responsiveness is improved, but task distribution complexity increases

Engineering Contradiction:
Improvesystem responsivenessVSAvoidtask distribution complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A task distribution manager is introduced as an intermediary component that resides on each processor but coordinates task allocation centrally. This mediator handles the complexity of task distribution and processor coordination, allowing the operating system to run responsively on multiple processors without exposing the complexity of task management to the rest of the system.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Stability of the object's composition

If TLB entries are flushed for all processors, then consistency is maintained, but performance degradation occurs

Engineering Contradiction:
ImproveTLB consistencyVSAvoidprocessor performance
Core Design Contradiction:
Stability of the object's compositionVSProductivity

Solution Approach 1:

The TLB flushing operation is made local to each processor by using processor-specific identifiers in TLB entries. Each processor can flush only its own associated entries rather than invalidating all entries in the shared TLB. This maintains consistency for each processor's translations while preserving performance by avoiding unnecessary flushes to other processors.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS7716673B2Tasks distribution in a multi-processor including a translation lookaside buffer shared between processors
Publication Date: 2010.05.11 TEXAS INSTRUMENTS INC
  • US7716673B2 patent drawing
  • US7716673B2 patent drawing
  • US7716673B2 patent drawing

AI summary

A system comprises a first processor, a second processor coupled to the first processor, an operating system that executes exclusively only on the first processor and not on the second processor, and a middle layer software running on the first processor and that distributes tasks to run on either or both processors. A synchronization unit coupled to the first and second processors also may be provided to synchronize the processors. Further still, a translation lookaside buffer may be included that is shared between the processors. Each entry in the translation lookaside buffer (“TLB”) may include a task identifier to permit the operating system or middle layer software to selectively flush only some of the TLB entries (e.g., the entries pertaining to only one of the processors).