Shared Translation Look-Aside Buffer Thread Isolation
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Solution Overview
Problem
In shared translation look-aside buffer systems, address translation for one thread can be evicted by another, leading to severe errors, and existing solutions either require complex and inefficient dedicated hardware or costly per-thread TLBs.
Innovation Solution
A software-managed shared translation look-aside buffer with thread-specific areas for temporary storage during exceptions and interrupts, allowing safe handling and restoration of register data to prevent eviction and ensure accurate address translation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a shared translation look-aside buffer is used between multiple processor threads, then cost and power consumption are reduced, but address translation for one thread can be evicted by another thread causing severe errors
Solution Approach 1:
The patent divides the shared TLB into thread-specific sections or uses thread identifiers to partition TLB entries, allowing each thread to have its own designated storage area within the shared buffer. This segmentation prevents one thread from evicting another thread's translations while still sharing the physical buffer resource, resolving the contradiction between cost reduction and translation reliability.
Solution Approach 2:
The patent introduces thread identifiers or context tags as intermediaries between the TLB and processing threads. These intermediaries allow the shared TLB to distinguish between different threads' translation requests and prevent unauthorized eviction, maintaining reliability while enabling sharing. The intermediary mechanism ensures that each thread's translations are protected from being incorrectly removed by other threads.
2Speed
If dedicated hardware is used to handle translation look-aside buffer misses, then handling is faster, but hardware complexity and cost increase
Solution Approach 1:
The patent designs the TLB hardware to perform multiple functions: it can operate in both hardware-managed and software-managed modes, handle both hits and misses, and support both shared and private configurations. This multi-functionality allows the same hardware structure to provide fast handling when needed while avoiding the need for separate specialized hardware components, thus reducing overall complexity while maintaining speed performance.
Solution Approach 2:
The patent implements dynamic configuration capabilities where the TLB can switch between different management modes (hardware vs. software) and configurations (shared vs. private) based on system needs. This dynamic adaptability allows the system to optimize for speed when performance is critical while falling back to simpler software management when complexity needs to be reduced, resolving the contradiction between speed and complexity.
3Reliability
If a translation look-aside buffer is provided for each processing thread, then address translation reliability is improved, but cost and efficiency deteriorate
Solution Approach 1:
The patent merges multiple thread-specific TLB functions into a single shared physical buffer structure. By combining the storage resources of what would otherwise be separate per-thread TLBs into one shared buffer with logical partitioning, the system achieves the reliability of thread-specific translations while reducing the total quantity of TLB hardware needed, thus resolving the contradiction between reliability and resource consumption.
Solution Approach 2:
The patent introduces a new dimension of thread identification and virtualization to the TLB structure. Instead of creating separate physical buffers for each thread (one-dimensional separation), the system uses a shared buffer with multi-dimensional addressing that incorporates thread identifiers, allowing logical separation while physical sharing. This dimensional approach maintains reliability through thread-specific logical spaces while reducing overall hardware quantity.
Data Source
AI summary
A shared translation look-aside buffer method comprises saving data stored in a first selected set of registers to a predetermined section of a thread-specific area in memory upon encountering an exception/interrupt, re-enabling exceptions and optionally interrupts, addressing a cause of the exception/interrupt while safely permitting another exception, and restoring the saved data to the first selected set of registers.