Shared Top Plate MIM Capacitor for Embedded RAM in SoC
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Solution Overview
Problem
The formation of MIM capacitors in semiconductor devices requires complex processing with three or more mask layers, leading to increased process cost and yield loss, necessitating a reduction in mask layers for improved throughput and cost-effectiveness.
Innovation Solution
A semiconductor device design featuring a substrate with an inter-layer dielectric layer, bottom plates, capacitor dielectric layers, and a shared top plate, where the top plate is formed over the capacitor dielectric layers and patterned to expose the inter-layer dielectric layer, reducing the need for multiple mask layers through a method involving conformal layer formation and selective patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MIM capacitor formation process is used, then reliable charge storage is achieved, but process complexity increases with three or more mask layers
Solution Approach 1:
The patent combines multiple capacitor structures under a single shared top plate, merging what would traditionally require separate processing into a unified structure. This reduces the number of mask layers needed while maintaining reliable charge storage functionality across multiple capacitors.
Solution Approach 2:
The shared top plate serves multiple capacitors simultaneously, making a single structure perform multiple functions. This universal approach allows one top plate to cap several bottom plates and dielectric layers, reducing overall process complexity and mask layer requirements.
2Manufacturing precision
If three or more mask layers are used for MIM capacitor formation, then complete capacitor structure is formed, but throughput decreases and process cost increases
Solution Approach 1:
Multiple capacitor formations are merged into a single processing step by using a shared top plate that covers multiple capacitors simultaneously. This consolidation reduces the number of sequential mask layers required, thereby increasing fabrication throughput without sacrificing structural completeness.
Solution Approach 2:
The method performs preliminary formation of multiple bottom plates and dielectric layers before adding the shared top plate. This preliminary arrangement allows subsequent processing to be simplified and accelerated, improving overall throughput while ensuring complete capacitor structures.
3Manufacturing precision
If complex processing with multiple mask layers is used, then precise capacitor formation is achieved, but yield loss increases
Solution Approach 1:
By merging multiple capacitor formations under one shared top plate, the patent reduces the total number of processing steps and mask layers. This consolidation minimizes the cumulative yield loss that would occur with multiple separate processing steps, while still achieving precise capacitor formation through the unified structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces process complexity, lowers costs, and enhances throughput by minimizing the number of mask layers required, while maintaining or improving the performance of embedded memories.
Implementation Method 1
Capacitors essentially comprise two conductive plates separated by a dielectric material. The capacitance, or amount of charge held by the capacitor per applied voltage, depends on a number of parameters such as the area of the plates, the distance between the plates, and the dielectric constant value for the dielectric material between the plates
Implementation Method 2
Capacitors essentially comprise two conductive plates separated by a dielectric material. The capacitance, or amount of charge held by the capacitor per applied voltage, depends on a number of parameters such as the area of the plates, the distance between the plates, and the dielectric constant value for the dielectric material between the plates
Data Source
AI summary
Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.