Shared Modulator-Demodulator Transceiver Without PLL Clocking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current transceivers require significant area and power due to separate modulation and demodulation circuits and a Phase-Locked Loop (PLL) clock source, leading to high power consumption and reduced effectiveness in low-power states, especially during channel direction reversals.
Innovation Solution
A transceiver design that integrates modulation and demodulation circuits without an external clock source, sharing common circuit elements and utilizing a single delay line as a ring oscillator for both functions, eliminating the need for a PLL and allowing for reversible channel direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate modulation and demodulation circuits with a PLL clock source are used, then the transceiver achieves reliable modulation and demodulation functions, but the area and power consumption increase significantly
Solution Approach 1:
The patent combines separate modulation and demodulation circuits into a single integrated transceiver circuit. The modulator and demodulator share common functional blocks including delay elements, multiplexers, and logic circuits, eliminating the need for separate dedicated circuits for each function.
Solution Approach 2:
The patent implements a universal delay line structure that serves both modulation and demodulation functions. The same delay elements and control logic are reused for both transmitting and receiving operations, allowing a single circuit to perform multiple functions that traditionally required separate dedicated circuits.
2Stability of the object's composition
If a Phase-Locked Loop (PLL) is used as clock source, then the modulation circuit achieves stable clock frequency, but the lock time is relatively long reducing effectiveness during low-power state
Solution Approach 1:
The patent extracts and eliminates the PLL clock source from the transceiver circuit. Instead of using a PLL to generate stable clock frequencies, the design uses direct digital synthesis techniques with delay lines and feedback mechanisms that do not require a PLL, thereby removing the lock time bottleneck.
Solution Approach 2:
The transceiver circuit uses self-generated timing signals through feedback loops rather than relying on an external PLL clock source. The delay line-based timing generation uses the circuit's own operational characteristics to establish stable timing without requiring a separate clock synchronization process.
3Adaptability or versatility
If separate modulation and demodulation circuits are used, then each circuit can be optimized independently, but the overall device complexity and shoreline increase
Solution Approach 1:
The patent merges separate modulation and demodulation circuits into an integrated architecture where common functional blocks are shared. The delay lines, multiplexers, and control logic are unified between transmit and receive paths, reducing overall circuit complexity while maintaining the ability to optimize performance.
Data Source
Figure 1~5
Figure 2A~3A2
Figure 2B
AI summary
A transceiver, including a modulation circuit configured to modulate a first digital word into a first modulated time signal; and a demodulation circuit configured to demodulate a second modulated time signal into a second digital word, wherein the modulation and demodulation circuits are operable without an external clock source, and inseparably share one or more same circuit elements. Also, a tunable delay line may be configured to set a time rate of the modulation, wherein the modulation circuit and the demodulation circuit inseparably share the tunable delay line.