Shared Transfer Latches for Non-Volatile Memory Area Reduction
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Solution Overview
Problem
The area devoted to read and write circuitry in non-volatile memory devices is significant, reducing the capacity for memory cells and affecting storage density, as the number and arrangement of data latches consume a substantial portion of the memory die.
Innovation Solution
The proposed solution involves sharing data latches between multiple columns, reducing the number of transfer latches and utilizing a shared set of transfer latches to transfer data between columns, thereby minimizing the area used by the latch structure and optimizing the use of the memory die for memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate transfer latches are provided for each column, then data transfer reliability is improved, but the area consumed by latch structure increases
Solution Approach 1:
The patent merges the transfer latches of multiple columns into a shared resource. Specifically, transfer latches are shared between an even column and an odd column, reducing the total number of transfer latches from N (one per column) to N/2 (shared between pairs of columns). This combining approach maintains data transfer reliability through proper timing control while significantly reducing the area consumed by the latch structure.
Solution Approach 2:
The patent implements multi-functionality by designing transfer latches that serve multiple columns simultaneously. A single set of transfer latches performs the data transfer function for both even and odd columns at different time intervals, making the latch structure universal rather than dedicated to a single column. This increases resource utilization efficiency and reduces overall latch area.
2Productivity
If more data latches are provided for each column, then read and write performance is improved, but the area devoted to peripheral elements increases
Solution Approach 1:
The patent combines the data latch resources of multiple columns into shared structures. By having even and odd columns share transfer latches and other peripheral elements, the total number of latches required is reduced while maintaining the ability to service multiple columns. This merging strategy preserves read and write performance through parallel operation capabilities while reducing peripheral area consumption.
Solution Approach 2:
The patent introduces dynamic timing control to manage shared latch resources. Control circuits dynamically allocate shared transfer latches to different columns based on operation timing - even columns operate during one time interval while odd columns operate during another. This dynamic time-division multiplexing maintains high data transfer rates and performance while reducing the static area requirement for peripheral elements.
3Area of stationary object
If transfer latches are shared between columns, then area efficiency is improved, but data transfer complexity increases
Solution Approach 1:
The patent segments the column operations into distinct time intervals - even columns are serviced during one time period while odd columns are serviced during another. This temporal segmentation simplifies the control logic for shared transfer latches by creating clear, non-overlapping operation windows. The segmentation approach reduces the complexity of managing shared resources compared to simultaneous multi-column access.
Solution Approach 2:
The patent implements periodic action through alternating operation cycles for even and odd columns. The shared transfer latches operate in a periodic manner, switching between serving even columns and odd columns in regular intervals. This periodic timing pattern simplifies control circuit design compared to arbitrary or simultaneous access schemes, as it establishes predictable, repeating operation sequences that are easier to manage.
Data Source
AI summary
In non-volatile memory circuit, the area devoted to the cache buffer of the read and write circuitry is reduced through the sharing of data latches. In an array structure where memory cells are connected along bit lines, and the bit lines organized into columns, each of the columns has an associated set of data latches, including one or more data latches for each bit line of the column. Data is transferred in and out of the read and write circuit on a data bus, where data is transferred between the data latches and the data bus through a set of transfers latches. The area used by the latch structure is reduced by sharing the transfer latches of the read and write circuitry between the data latches of multiple columns.