Shared-Transistor Decoder Circuits for Low-Power, High-Speed Operation

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Solution Overview

Problem

Existing decoder circuits in semiconductor devices occupy significant circuit area and consume high power, limiting their efficiency and speed.

Innovation Solution

Implementing decoder circuits using shared transistors, particularly in NAND and NOR configurations, to reduce the number of transistors required while maintaining functionality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional decoder circuits are used, then functionality is maintained, but circuit area and power consumption increase

Engineering Contradiction:

Improvenumber of transistorsVSAvoidcircuit area

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

Multiple decoder circuits share common transistors to reduce the total number of transistors required. For example, decoders D1 and D2 share transistors T1-T4, and decoders D3 and D4 share transistors T5-T8, thereby reducing circuit area and transistor count while maintaining full functionality

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Transistors are designed to serve multiple functions across different decoder circuits. The same transistor serves as part of multiple decoder units, enabling resource sharing and reducing the overall quantity of components needed in the system

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Quantity of substance

If traditional decoder circuits are used, then functionality is maintained, but power consumption increases

Engineering Contradiction:

Improvenumber of transistorsVSAvoidpower consumption

Core Design Contradiction:

Quantity of substanceVSUse of energy by stationary object

Solution Approach 1:

By merging multiple decoder circuits into a shared transistor architecture, the total power consumption is reduced because fewer transistors are actively consuming power. The shared transistor structure ensures that power is not wasted in redundant components while maintaining all necessary decoding functions

Inventive Principle:

Principle #5Merging (Combining)

3Quantity of substance

If traditional decoder circuits are used, then functionality is maintained, but operational speed decreases

Engineering Contradiction:

Improvenumber of transistorsVSAvoidoperational speed

Core Design Contradiction:

Quantity of substanceVSSpeed

Solution Approach 1:

The shared transistor configuration reduces the number of signal propagation paths and decreases the overall circuit delay. With fewer transistors in the critical paths and reduced interconnect length, the decoder circuits achieve higher operational speed while maintaining full functionality

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12374376B2Decoder circuits using shared transistors for low-power, high-speed, and small area

Publication Date: 2025.07.29 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Decoder devices and a method of operating word-line decoder devices are disclosed. In one aspect, a decoder device includes a first logic gate that receives a disable signal and a first input signal, and generates a first decoder output signal at a first output node. The decoder device includes a second logic gate that receives the disable signal and a second input signal, and generates a second decoder output signal at a second output node. The first logic gate and the second logic gate share a transistor. The transistor has a first terminal coupled to the first output node, a second terminal coupled to the second output node, and a gate terminal that receives the disable signal.