Shared Transistor Magnetic Recording Array Integration

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Solution Overview

Problem

Three-terminal type spin elements require multiple transistors for controlling writing and reading currents, leading to increased area requirements and reduced integration in magnetic recording arrays.

Innovation Solution

A magnetic recording array with shared transistors connected to adjacent spin elements, utilizing a laminate structure with ferromagnetic layers and non-magnetic layers, and wiring that generates a spin current through the spin Hall effect, allowing for reduced transistor area and increased integration by sharing transistors between spin elements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If multiple transistors are used to control writing and reading currents in three-terminal type spin elements, then the control functionality is improved, but the area required for each spin element increases

Engineering Contradiction:
Improvecontrol functionalityVSAvoidarea per spin element
Core Design Contradiction:
Ease of operationVSArea of stationary object

Solution Approach 1:

The patent merges the control functions of multiple transistors into a shared transistor structure. The shared transistor has multiple gates (first gate, second gate, third gate) that collectively control writing and reading currents for multiple spin elements, replacing what would traditionally require separate transistors for each spin element. This merging reduces the total transistor count and area while maintaining full control functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared transistor is designed with multi-functionality to control both writing and reading operations for multiple spin elements simultaneously. The multiple gates of the shared transistor can be selectively activated to perform different control functions, making a single transistor structure serve the role of multiple transistors would traditionally need to perform.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Area of stationary object

If a shared transistor structure is used to reduce area, then integration density is improved, but the transistor control complexity increases

Engineering Contradiction:
Improvearea per spin elementVSAvoidtransistor structure complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The shared transistor is segmented into multiple independent gates (first gate, second gate, third gate), each capable of being controlled independently. This segmentation allows the complex control functions to be divided into manageable gate control operations, where each gate handles specific control tasks, simplifying the overall control logic despite the multi-gate structure.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enhances integration density in magnetic recording arrays by reducing the area required for transistors, enabling higher recording density and efficient data writing and reading operations.

Implementation Method 1

the wiring may be any of a metal, an alloy, an intermetallic compound, a metal boride, a metal carbide, a metal silicide, and a metal phosphide that have a function of generating a spin current by the spin Hall effect when an electric current flows

Methodology Applied
Scientific EffectSpin Hall effect: Hall Effect

Data Source

PatentUS11948615B2Magnetic recording array
Publication Date: 2024.04.02 TDK CORP
  • US11948615B2 patent drawing
  • US11948615B2 patent drawing
  • US11948615B2 patent drawing

AI summary

A magnetic recording array includes a plurality of spin elements, and a shared transistor connected to a first spin element and a second spin element adjacent to each other, in which each of the plurality of spin elements includes a wiring and a laminate including a first ferromagnetic layer laminated on the wiring, the shared transistor includes a first gate, a second gate, a first region, a second region, and a third region, in a plan view in a laminating direction of the laminate, the first region is sandwiched between the first gate and the second gate, the second region together with the first region sandwiches the first gate, and the third region together with the first region sandwiches the second gate, and one of the second region and the third region is connected to the first spin element, and the other is connected to the second spin element.