Shared Transistor STTMRAM Cell Architecture
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Solution Overview
Problem
Current spin-transfer torque magnetic random access memory (STTMRAM) cells have large footprints due to the requirement of one transistor per magnetic tunnel junction (MTJ), leading to inefficient switching current density and unreliable read operations, which are exacerbated by the need for high switching currents that can alter the MTJ state during read operations.
Innovation Solution
A shared transistor configuration is implemented, where two neighboring MTJs share access transistors, allowing half of the switching current to be provided by each neighboring MTJ, reducing the memory cell size to 12F^2 and increasing switching current density while minimizing the impact on unselected MTJs during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If one transistor is allocated per MTJ in conventional STTMRAM cells, then each MTJ can be accessed independently, but the memory cell footprint becomes excessively large (greater than 20F^2)
Solution Approach 1:
Two neighboring MTJs share a common access transistor, merging the access control function for both MTJs into a single transistor. This sharing arrangement reduces the total transistor count per MTJ from one to 0.5, thereby shrinking the memory cell footprint from greater than 20F^2 to 12F^2 while maintaining independent access capability through selective transistor activation
Solution Approach 2:
The shared access transistor serves multiple functions: it acts as the access transistor for both MTJ1 and MTJ2, and can be selectively activated to access either MTJ independently. This multi-functional design eliminates the need for separate dedicated transistors for each MTJ, achieving area reduction without sacrificing access independence
2Reliability
If high switching current is applied to switch MTJ state, then writing operation is effective, but the MTJ state may be undesirably altered during read operations
Solution Approach 1:
The bit line current is segmented and distributed to multiple MTJs through the shared transistor configuration. During write operations, current is routed through specific MTJ paths to achieve effective switching. During read operations, the same shared transistor structure enables current division such that the read current is split between MTJs, reducing the current density through any single MTJ and preventing unintended state changes
Solution Approach 2:
The patent utilizes different current magnitude parameters for write and read operations. Write current is set at high levels sufficient to switch MTJ magnetic states, while read current is set at low levels that do not cause switching. The shared transistor configuration inherently supports this parameter differentiation by providing current division paths, allowing the system to adapt current levels based on operation type without affecting MTJ state during reads
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves a smaller memory cell size and higher switching current density, enhancing reliability by reducing the current required for writing and ensuring that the MTJ state is not altered during read operations, thus improving data integrity and scalability.
Implementation Method 1
spin transfer torque magnetic random access memory (STTMRAM)
Data Source
AI summary
A spin-torque transfer memory random access memory (STTMRAM) cell is disclosed comprising a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ.