Shared-Trench MOSFET-Schottky Layout for Smaller Power Chips
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Solution Overview
Problem
Conventional methods for integrating trench MOS barrier Schottky (TMBS) diodes and shielded gate trench MOSFETs (SGT MOSFETs) in semiconductor power circuits require additional chip area, leading to inefficiencies and increased production costs, as they are typically placed in adjacent areas on the same chip.
Innovation Solution
A trench semiconductor structure is designed with minimized spacing between TMBS and SGT MOSFET, integrating them within the same trench, utilizing a semiconductor material layer with specific trench structures, electrodes, gates, oxide layers, and doped regions, and including a shielding metal layer to enhance electrical connectivity and reduce chip area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If TMBS and SGT MOSFET are placed in adjacent areas on the same chip, then both devices can be integrated, but additional chip area is required leading to increased production costs
Solution Approach 1:
The patent merges the TMBS diode and SGT MOSFET into a single shared trench structure. The trench contains both a first electrode forming a Schottky contact with the semiconductor layer (for TMBS) and a second electrode forming a gate (for MOSFET), along with a gate insulating layer separating them. This spatial merging allows both devices to coexist in the same trench footprint, eliminating the need for separate adjacent trenches and thereby reducing the total chip area required for integration.
Solution Approach 2:
The patent implements a nested configuration where the TMBS diode structure is embedded within the same trench that houses the SGT MOSFET gate structure. The first electrode (Schottky contact) and second electrode (gate) are nested within the shared trench, with the gate insulating layer providing separation. This nesting approach allows one device structure to be contained within the spatial envelope of the other, maximizing space utilization and minimizing chip area.
2Adaptability or versatility
If conventional adjacent placement is used, then device integration is achieved, but manufacturing complexity and production costs increase
Solution Approach 1:
The patent combines multiple manufacturing steps into a unified process. A single trench is formed using one etching process, and both the gate insulating layer and electrodes are deposited and patterned within this shared trench structure. This merging of manufacturing operations reduces the total number of separate process steps compared to fabricating adjacent trenches independently, thereby simplifying the overall manufacturing complexity and reducing production costs.
Solution Approach 2:
The shared trench structure serves multiple functions simultaneously: it acts as the confinement structure for the SGT MOSFET gate, provides the Schottky contact formation region for the TMBS diode, and houses both electrodes and insulating layers. This multi-functionality of a single trench structure eliminates the need for separate trenches for each device, reducing manufacturing steps and simplifying the fabrication process.
3Reliability
If TMBS and SGT MOSFET are integrated in separate trenches, then device performance is maintained, but chip area utilization is inefficient
Solution Approach 1:
The patent merges the functional structures of TMBS and SGT MOSFET into a single trench while maintaining their electrical independence through the gate insulating layer. The first electrode forms a Schottky contact for the TMBS diode, while the second electrode forms the gate for the MOSFET, with both structures sharing the same trench confinement. This merging maintains the essential performance characteristics of both devices while achieving superior chip area utilization compared to separate trench configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This integration minimizes chip area utilization, improves device performance by reducing resistance and gate capacitance, and enhances switching speed while maintaining high power and low loss characteristics.
Implementation Method 1
a first oxide layer separating the first electrode from the first gate
Implementation Method 2
a first doped region located in the semiconductor material layer adjacent to the first surface and adjacent to the first portion of the first electrode, wherein the first doped region has a second conductivity type
Implementation Method 3
The charge coupling redistributes the electric field below the Schottky contact, thereby improving the breakdown voltage
Data Source
AI summary
A trench semiconductor structure includes a semiconductor material layer having a first surface and a second surface. A first trench structure extends from the first surface towards the second surface, and includes an electrode and a gate. The electrode includes a first portion and a second portion below the first portion and the gate. An interlayer dielectric layer is disposed on the first surface covering the first trench structure and a doped region in the semiconductor material layer. A shielding metal layer covers the interlayer dielectric layer and the fist doped region and contacts the electrode. A metal layer is disposed on the shielding metal layer. The first portion of the first electrode is located between the doped region and the gate. The electrode and the doped region contact the shielding metal layer and are electrically connected to the metal layer.