Shared Unity Gain Buffer in PLL Charge Pump and Loop Filter
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Solution Overview
Problem
Continuous-time delta-sigma modulator based ADCs in RF receiver applications face challenges with high power consumption and large die area due to non-optimized phase-locked loops (PLLs), which complicate modem design and increase costs.
Innovation Solution
A phase-locked loop (PLL) is designed to provide a fixed-rate clock for ADCs, incorporating a charge pump, active loop filter, and unity gain buffer to reduce power consumption and simplify modem design, with power scaling based on input signal strength and clock rate, and utilizing multiple voltage control oscillators (VCOs) to adjust jitter and power usage accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a dedicated PLL is used to generate fixed-rate clock for ADC, then modem design is simplified, but power consumption increases
Solution Approach 1:
The unity gain buffer is shared between the charge pump and the active loop filter, merging one circuit component to serve dual purposes. This reduces the total number of components needed in the PLL, thereby reducing power consumption while maintaining the fixed-rate clock generation function that simplifies modem design.
Solution Approach 2:
The unity gain buffer performs multiple functions: it operates as part of the charge pump circuitry and simultaneously serves as part of the active loop filter. This multi-functionality eliminates the need for separate buffer circuits, reducing overall power consumption while preserving the PLL's ability to provide a stable fixed-rate clock.
2Ease of operation
If a dedicated PLL is used to generate fixed-rate clock for ADC, then modem design is simplified, but die area increases
Solution Approach 1:
The unity gain buffer is merged into a single circuit that serves both the charge pump and active loop filter functions. This consolidation reduces the total circuit area required for the PLL, thereby reducing die area while maintaining the fixed-rate clock generation capability that simplifies modem design.
Solution Approach 2:
The shared unity gain buffer performs dual functions in two different circuit blocks (charge pump and loop filter), eliminating the need for separate buffer circuits and reducing the overall die area occupied by the PLL while preserving its clock generation function.
3Reliability
If active loop filter is used with increased effective capacitance, then loop filter performance is improved, but power consumption increases
Solution Approach 1:
The unity gain buffer is shared between the charge pump and active loop filter, allowing the loop filter to achieve increased effective capacitance and improved performance without requiring a completely separate buffer circuit. This sharing arrangement reduces the total power consumption compared to having dedicated buffers for each function.
Data Source
AI summary
A unity gain buffer is shared by a charge pump and an active loop filter in a phase-locked loop. The charge pump uses the unity gain buffer to reduce current mismatch in the charge pump and the active loop filter uses the unity gain buffer in a circuit that increases the effective capacitance of the active loop filter.


