Shared-VCO Impedance Measurement for Stable Power Delivery Networks
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Solution Overview
Problem
High-performance computing (HPC) circuits face challenges in power delivery network (PDN) stability due to power or ground bounce, leading to signal integrity issues and electromagnetic interference (EMI), with existing power impedance measurement (PIM) circuits facing timing issues and area overhead from additional voltage controlled oscillators (VCOs).
Innovation Solution
A dual-mode impedance measurement system employing equivalent-time sampling (ETS) and built-in self-test (BIST) circuits for accurate power impedance measurement, utilizing time-domain and frequency-domain sensing to model power delivery networks, reducing redundancy and area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If power impedance measurement circuits are added to ensure stable PDN operation, then measurement accuracy and PDN stability are improved, but area overhead and timing issues increase due to additional voltage controlled oscillators
Solution Approach 1:
The patent combines the voltage controlled oscillator (VCO) with the power impedance measurement circuit into a unified structure. The VCO is shared between the BIST function for impedance measurement and the normal operating function, eliminating the need for separate additional VCOs and reducing area overhead while maintaining measurement accuracy
Solution Approach 2:
The VCO is designed to serve multiple functions: it operates as part of the BIST circuit for power impedance measurement and simultaneously functions during normal circuit operation. This multi-functionality reduces the total number of oscillators needed and decreases area overhead
2Productivity
If trigger time and sampling time are set close together for fast measurement, then measurement speed is improved, but timing issues and signal integrity problems occur
Solution Approach 1:
The patent implements a dynamic timing adjustment mechanism that automatically optimizes the time interval between trigger and sampling based on circuit conditions. The timing is not fixed but can be adjusted to balance measurement speed with timing accuracy, preventing signal integrity issues while maintaining fast measurement capability
Solution Approach 2:
The BIST circuit incorporates feedback mechanisms that monitor timing conditions and adjust the trigger-sampling interval accordingly. When timing issues are detected, the system adjusts the timing parameters to maintain accuracy while minimizing impact on measurement speed
3Productivity
If HPC circuits operate at high speeds with large current to process large datasets, then computing performance is improved, but power bounce and ground bounce increase causing signal integrity issues
Solution Approach 1:
The patent implements preliminary characterization of the power delivery network through BIST measurements during manufacturing. This early assessment allows identification of PDN weaknesses before the product is deployed, enabling proactive compensation measures to be implemented in the circuit design to mitigate power and ground bounce during high-speed operation
Solution Approach 2:
The system performs self-diagnosis and self-characterization of its power delivery network through built-in self-test circuits. The HPC circuit itself generates the test signals and measurements needed to assess its own PDN performance, eliminating the need for external testing equipment and enabling continuous monitoring of power bounce conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system provides high bandwidth and accuracy for power impedance measurement, ensuring stable PDN operation by efficiently estimating power voltage drops, reducing area and power consumption, and minimizing signal integrity issues.
Implementation Method 1
a voltage controlled oscillator (VCO), generating an oscillation signal according to a power voltage on the power rail
Implementation Method 2
an operation circuit, coupled to the VCO, receiving a sampling clock signal and the oscillation signal, sensing the power voltage to generate a sampled signal based on the sampling clock signal
Implementation Method 3
accumulating the sampled signal to generate a measurement result
Data Source
AI summary
An impedance measurement circuit and an operating method thereof are provided. The impedance measurement circuit includes a current source, a voltage controlled oscillator (VCO), an operation circuit, and a first delay circuit. The current source, electrically connected to a power rail, is able to sink a current from the power rail according to the delayed clock signal. The VCO is configured to generate an oscillation signal according to a power voltage on the power rail. The operation circuit is electrically connected to the VCO and is configured to receive a sampling clock signal and the oscillation signal, sense the power voltage to generate a sampled signal, and accumulate the sampled signal to generate a measurement result. The first delay circuit, electrically connected to the current source and the operation circuit, is able to receive the sampling clock signal and transmit the delayed clock signal to the current source.