Shared Verify Voltage for Multi-Level Cell Memory Programming

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Solution Overview

Problem

Multi-level cell memory devices, such as quad-level cell (QLC) NAND devices, face performance issues due to the need for numerous program pulses and verify operations, which slow down programming speed because of the requirement for precise threshold voltage spacing between memory cells.

Innovation Solution

Implementing a control circuitry that applies a shared verify voltage level to verify multiple program voltage levels, reducing the number of verification operations by comparing bitline currents to reference currents, thereby streamlining the programming and verification process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple verify voltage levels are applied to verify each program voltage level, then verification accuracy is improved, but verification time increases

Engineering Contradiction:

Improveverification accuracyVSAvoidverification time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent merges the verification process by applying a single shared verify voltage level to verify multiple consecutive program voltage levels simultaneously. Instead of applying separate verify voltage levels for each program level, the invention combines these operations into one unified verification step, thereby reducing verification time while maintaining accuracy through comparative bitline current measurements against multiple reference currents.

Inventive Principle:

Principle #5Merging (Combining)

2Quantity of substance

If the number of program voltage levels is increased to enhance storage capacity, then memory density is improved, but programming speed deteriorates

Engineering Contradiction:

Improvestorage capacityVSAvoidprogramming speed

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The invention merges multiple verification operations into a single operation by applying one shared verify voltage level to verify multiple program voltage levels concurrently. This reduces the total number of verify operations required, thereby improving programming speed while maintaining the high storage capacity enabled by multiple program voltage levels in QLC and other multi-level memory devices.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the verification approach by using a shared verify voltage level instead of multiple distinct verify voltage levels. By modifying the verification parameter from multiple voltage levels to a single voltage level with multiple reference currents, the invention reduces verification overhead and improves programming speed while preserving the ability to verify multiple program levels accurately.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10832766B2Program verification time reduction in non-volatile memory devices

Publication Date: 2020.11.10 INTEL NDTM US LLC

AI summary

An apparatus and/or system is described including a memory device or a controller to perform programming and verification operations including application of a shared voltage level to verify two program voltage levels of a multi-level cell device. For example, in embodiments, the control circuitry performs a program operation to program a memory cell and performs a verification operation by applying a single or shared verify voltage level to verify that the memory cell is programmed to a corresponding program voltage level. In embodiments, the program voltage level is one of two consecutive program voltage levels of a plurality of program voltage levels to be verified by application of the shared verify voltage. Other embodiments are disclosed and claimed.