Shared Vertex and Geometry Shader Cache with Virtual Spaces
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Solution Overview
Problem
Conventional vertex caches in graphics pipelines face issues such as high latency and stalling due to differing access patterns between vertex shader and geometry shader units, leading to inefficient cache utilization and increased costs when trying to increase cache size.
Innovation Solution
Implementing a shared cache system with virtual and physical cache layers, where virtual cache spaces of different sizes map to a physical cache, allowing flexible buffer sizes and prioritizing data based on distance to consumption, thereby reducing latency and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the cache size is increased by increasing the number of lines, then the cache hit rate is improved, but the hardware cost increases due to more cache tags and comparators being needed
Solution Approach 1:
The patent segments the cache into two distinct types: a vertex cache for vertex shader operations and a geometry cache for geometry shader operations. This segmentation allows each cache to be optimized for its specific workload patterns, achieving higher hit rates without requiring a monolithic large cache that would increase hardware cost proportionally.
Solution Approach 2:
The patent applies local quality by providing different cache configurations tailored to the specific needs of vertex shaders and geometry shaders. Each cache type has parameters (size, associativity, replacement policy) optimized for its particular access patterns, rather than using a uniform cache design that would waste resources on one type of shader while insufficiently serving another.
2Loss of time
If the cache size is increased, then the latency compensation is improved, but the cache tags and comparators cost more
Solution Approach 1:
By segmenting the cache into vertex and geometry-specific caches, the patent reduces the size needed for each individual cache while maintaining overall latency compensation capability. Each smaller cache can be filled more quickly and has fewer tags and comparators, reducing the time penalty associated with cache misses while still providing sufficient buffering to mask latency during shader execution.
3Productivity
If pre- and post-reference counters are used to allow multiple misses, then the vertex shader execution can proceed without waiting for all reads to finish, but the vertex shader execution must be performed in order and data must be updated in the cache in order
Solution Approach 1:
The patent segments the reference counting mechanism into separate pre-reference counters and post-reference counters for each cache line. This allows independent management of read requests and write completions, enabling the vertex shader to proceed with multiple misses while maintaining proper ordering through the structured counter system. The pre-counters track pending reads and the post-counters track completed writes, allowing parallel processing without violating operational constraints.
4Quantity of substance
If the cache size is fixed with a given number of sets, then the tag field and index field sizes are determined, but increasing the cache size requires adjusting the sizes of the index and tag fields
Solution Approach 1:
The patent segments the cache into separate vertex and geometry caches with independently configurable sizes. This allows the cache size to be increased by adding more sets to one cache without requiring proportional increases in field sizes for both caches. Each cache can be optimized with appropriate tag and index field sizes for its specific workload, avoiding the need to redesign the entire cache architecture when increasing capacity.
Data Source
AI summary
Systems and methods for sharing a physical cache among one or more clients in a stream data processing pipeline are described. One embodiment is directed to a system for sharing caches between two or more clients. The system comprises a physical cache memory having a memory portion accessed through a cache index. The system further comprises at least two virtual cache spaces mapping to the memory portion, each of the virtual cache spaces has an active window which has a different size than the memory portion. Further, the system comprises at least one virtual cache controller configured to perform a hit-miss test on the active window of the virtual cache space in response to a request from one of the clients for accessing the physical cache memory. Furthermore, data is accessed from the corresponding location of the memory portion when the hit-miss test of the cache index returns a hit.