Shared Virtual Address Spaces for Multi-Domain Memory Access

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Solution Overview

Problem

Existing memory systems are limited by the amount of accessible memory due to host-managed coherency in single domains, restricting the use of a global address space across multiple memory systems.

Innovation Solution

A system utilizing a variable width virtual device identifier and parameters for globally shared address spaces, allowing address translations on a per-device basis and enabling access to larger memory spaces across multiple domains.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If host-managed coherency is used in single domains, then memory coherency is maintained, but accessible memory space is limited

Engineering Contradiction:
Improvememory coherencyVSAvoidaccessible memory space
Core Design Contradiction:
ReliabilityVSVolume of stationary object

Solution Approach 1:

The patent segments the address space into domain-local address spaces and a shared virtual address space. Each domain manages its own local memory coherency independently, while the shared virtual address space provides a common memory region accessible across multiple domains. This segmentation allows each domain to maintain coherency control without being constrained by the total accessible memory space, resolving the contradiction between coherency management and memory accessibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of address space hierarchy by enabling devices to access memory through multiple address space dimensions: domain-local address spaces for private coherency and a shared virtual address space for cross-domain access. This multi-dimensional address architecture allows the system to maintain coherency within domains while expanding accessible memory space across domains through the shared address space dimension.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Volume of stationary object

If a global address space is implemented across multiple memory systems, then accessible memory space increases, but address translation complexity increases

Engineering Contradiction:
Improveaccessible memory spaceVSAvoidaddress translation complexity
Core Design Contradiction:
Volume of stationary objectVSDevice complexity

Solution Approach 1:

The patent segments address translation into two distinct stages: first, domain-local address translation within each memory system, and second, shared virtual address space mapping. This segmentation reduces the translation complexity by handling address translation in smaller, more manageable units rather than performing a single complex global translation, thus enabling larger accessible memory spaces without proportionally increasing translation complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The shared virtual address space acts as an intermediary layer between domain-local address spaces and physical memory. This intermediary structure simplifies address translation by providing a standardized mapping mechanism that bridges multiple domains, reducing the complexity that would otherwise arise from direct multi-domain address translation while enabling access to expanded memory spaces.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If address translations are performed on a per-device basis, then device-specific memory access is optimized, but the number of address translations required increases

Engineering Contradiction:
Improvememory access performanceVSAvoidaddress translation time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments address translation into domain-local and shared components. Domain-local address translations are performed once during initialization to establish mappings between domain addresses and shared virtual addresses. Subsequent memory accesses use the pre-established shared virtual address mappings, eliminating the need for repeated per-device address translations and reducing translation time while maintaining optimized device-specific access paths.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs address translation preliminarily by establishing domain-local to shared virtual address mappings during system initialization or first access. This preliminary action caches the translation results, allowing subsequent memory accesses to skip the complex per-device translation process and directly use the pre-computed mappings, thus optimizing memory access performance while reducing the time cost of repeated address translations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250291734A1Shared virtual address spaces
Publication Date: 2025.09.18 MICRON TECHNOLOGY INC
  • US20250291734A1 patent drawing
  • US20250291734A1 patent drawing
  • US20250291734A1 patent drawing

AI summary

Methods, systems, and devices for shared virtual address spaces are described. In some examples, a globally shared address space may be shared across a plurality of memory devices that are included in one or more domains. A host system may set parameters for determining whether an address (e.g., a virtual address) is included within the globally shared address space, and whether the address is associated with a memory device. When a memory device receives a memory request (e.g., a data packet), a processing unit of the memory device may determine whether an address included in the memory request is associated with the memory device. The processing unit may either initiate an access operation on a physical address of the memory device or transmit the memory request to another memory device.