Shared Virtual Memory Management for Multi-Core Cache Coherence
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Solution Overview
Problem
In multi-core chip environments that do not support cache coherence, existing methods for ensuring data consistency across multiple cores are limited by increased communication overhead, leading to scalability issues and data inconsistency when multiple cores attempt to write to the same physical memory page.
Innovation Solution
A shared virtual memory management apparatus is implemented, comprising a shared virtual memory manager, a physical memory manager, and a memory mapper, which allocates separate physical memory pages to cores attempting to write to the same virtual memory page, updates these pages, and maps the changes to the original physical memory page, ensuring data consistency by setting the physical memory pages as uncacheable to prevent data inconsistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache coherence protocols are built into multicore chips to provide data coherence, then data consistency is improved, but device complexity and scalability deteriorate when the number of cores increases
Solution Approach 1:
The patent introduces a shared virtual memory manager as an intermediary layer between multiple cores and physical memory. This manager handles memory allocation, tracking, and consistency maintenance, replacing the need for complex hardware-based cache coherence protocols. The virtual memory manager acts as a mediator that coordinates access to shared memory pages, reducing direct communication overhead between cores while maintaining data consistency through software-based page fault handling and memory mapping mechanisms.
2Productivity
If the number of cores increases to improve processing power, then productivity is improved, but communication overhead increases leading to scalability limitations
Solution Approach 1:
The patent segments physical memory into discrete pages and introduces virtual memory pages as intermediate abstraction layers. Each core accesses memory through its own virtual address space, with the shared virtual memory manager managing page-level segmentation. This segmentation allows independent management of memory regions, reducing the need for global synchronization and communication overhead as core count increases, thereby improving scalability while maintaining high productivity.
3Adaptability or versatility
If software shared virtual memory is used to manage memory allocation, then adaptability is improved, but manufacturing precision and data consistency deteriorate without hardware cache coherence support
Solution Approach 1:
The patent implements feedback mechanisms through page fault handlers that monitor and track memory access patterns across multiple cores. When a core accesses a shared virtual memory page, the system generates page fault information that is processed to update the shared virtual memory manager's state. This feedback loop ensures that memory consistency is maintained through software-based tracking and updating of page permissions and mappings, providing data consistency comparable to hardware protocols while maintaining software flexibility.
Data Source
AI summary
A shared virtual memory management apparatus for ensuring cache coherence. When two or more cores request write permission to the same virtual memory page, the shared virtual memory management apparatus allocates a physical memory page for the cores to change data in the allocated physical memory page. Thereafter, changed data is updated in an original physical memory page, and accordingly it is feasible to achieve data coherence in a multi-core hardware environment that does not provide cache coherence.