Shared Virtual Memory for Heterogeneous CPU-GPU Pointer Translation

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Solution Overview

Problem

OpenCL framework does not allow seamless sharing of complex data structures between multiple heterogeneous devices, requiring complex decoding of offsets and binding tables for CPU to GPU pointer translation.

Innovation Solution

A method and apparatus for facilitating shared pointers in a heterogeneous platform by extending the C programming language to support a shared virtual memory (SVM) model, allowing direct sharing of CPU pointers with GPU devices through a compiler code generation scheme that adjusts virtual addresses for both devices to reference the same physical memory location.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If CPU pointer to GPU pointer translation is implemented using binding tables and offsets, then pointer sharing between CPU and GPU is enabled, but the complexity of the system increases due to multiple binding tables and decoding requirements

Engineering Contradiction:
Improvepointer sharing capabilityVSAvoidbinding table and offset decoding complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent extracts the complex binding table and offset decoding mechanism from the pointer translation process and replaces it with a simplified direct mapping approach. Each GPU memory region is assigned a unique base address that is directly added to CPU virtual addresses, eliminating the need for binding tables and offset calculations.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the parameter representation by introducing base addresses for GPU memory regions instead of using binding table indices and offsets. This parameter transformation simplifies the pointer translation from a multi-step decoding process to a single addition operation.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If seamless sharing of complex data structures is implemented, then productivity and ease of operation improve, but the device complexity increases due to shared virtual memory management

Engineering Contradiction:
Improvedata sharing efficiencyVSAvoidshared virtual memory management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a universal address space that allows both CPU and GPU to access the same memory regions using the same pointer representation. The shared virtual memory system provides a unified interface for data structures, enabling seamless sharing without requiring separate memory management mechanisms for different device types.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If virtual-to-physical mappings are made different across processing cores, then adaptability to heterogeneous devices improves, but the difficulty of pointer sharing increases

Engineering Contradiction:
Improveheterogeneous device compatibilityVSAvoidpointer sharing difficulty
Core Design Contradiction:
Adaptability or versatilityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent introduces base addresses as intermediary values that mediate between CPU virtual addresses and GPU physical addresses. Each GPU memory region has an associated base address that acts as a mediator, allowing direct addition to CPU pointers without requiring complex virtual-to-physical mapping translations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8862831B2Method and apparatus to facilitate shared pointers in a heterogeneous platform
Publication Date: 2014.10.14 INTEL CORP
  • US8862831B2 patent drawing
  • US8862831B2 patent drawing
  • US8862831B2 patent drawing

AI summary

A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.