Shared Voltage Selection Circuits for 3D NAND Memory Area Reduction
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Solution Overview
Problem
The challenge is to reduce the area of memory devices, particularly in three-dimensional NAND memory technology, where the existing designs face inefficiencies in voltage selection circuits that hinder miniaturization and performance during program and read operations.
Innovation Solution
The proposed solution involves a memory device with a memory cell array and peripheral circuits that include selected and unselected voltage selection circuits, global and local word line voltage selection circuits, which share resources during program and read operations, allowing for efficient voltage selection and reducing the overall area required for the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate voltage selection circuits are provided for each memory plane, then each plane can independently perform read operations, but the area of the memory device increases
Solution Approach 1:
The patent implements a shared voltage selection circuit that can be dynamically allocated to different memory planes based on operation type. During program operations, the shared circuit serves all memory planes simultaneously. During read operations, the shared circuit is divided among multiple memory planes, allowing each to perform independent reads without requiring dedicated circuits for each plane.
2Area of stationary object
If voltage selection circuits are shared among memory planes, then the area is reduced, but the circuit cannot simultaneously support program and read operations across all planes
Solution Approach 1:
The patent employs dynamic resource allocation where the shared voltage selection circuit's assignment changes based on the operation being performed. The system can dynamically switch between program mode (where all planes share the circuit) and read mode (where the circuit is divided among planes), allowing the hardware configuration to adapt to different operational requirements without physical reconfiguration.
Solution Approach 2:
The system alternates between different operational modes that require different circuit configurations. Program operations and read operations are performed in periodic sequences, with the voltage selection circuit reconfigured between operation types to optimize performance for the current operation while maintaining area efficiency through sharing.
3Productivity
If more voltage selection circuits are provided, then program and read operations can be performed simultaneously across multiple planes, but the device complexity and area increase
Solution Approach 1:
The patent merges the voltage selection functionality into a single shared circuit that handles both program and read operations for multiple memory planes. By combining what would traditionally be separate circuits into one unified resource that is time-multiplexed and dynamically allocated, the system achieves simultaneous operation capability across planes without proportionally increasing circuit quantity or device complexity.
Data Source
AI summary
A memory device includes a memory cell array including memory planes and a peripheral circuit coupled to the memory cell array. The peripheral circuit includes selected voltage selection circuits, global word line voltage selection circuits coupled to the selected voltage selection circuits, and local word line voltage selection circuits coupled to the global word line voltage selection circuits. Each memory plane corresponds to the plurality of selected voltage selection circuits. Each memory plane corresponds to respective global word line voltage selection circuits of the global word line voltage selection circuits. Each memory plane corresponds to respective local word line voltage selection circuits of the local word line voltage selection circuits. At least one of the selected voltage selection circuits is configured to apply a program voltage and a read voltage.