Shared Well Layout With Single Pickups for Latch-Up Protection

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Solution Overview

Problem

Existing integrated circuit (IC) designs face challenges in efficiently utilizing space for IC devices while providing latch-up protection, as they often require multiple pickup structures for each well corresponding to one or two rows of IC devices.

Innovation Solution

The proposed IC structure incorporates a shared well configuration between multiple rows of IC devices, utilizing a single pickup structure to bias each portion of the well, thereby reducing the number of pickup structures needed and increasing space utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple pickup structures are used for each well corresponding to one or two rows of IC devices, then latch-up protection is provided, but space utilization is reduced

Engineering Contradiction:
Improvelatch-up protectionVSAvoidspace utilization
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple wells into a shared well structure that serves multiple rows of IC devices. Instead of having separate wells for each row or pair of rows, a single shared well is formed that extends to serve multiple rows simultaneously. This consolidation reduces the total number of pickup structures needed while maintaining latch-up protection across all served rows, thereby improving space utilization without sacrificing reliability

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12288786B2Shared well structure manufacturing method
Publication Date: 2025.04.29 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12288786B2 patent drawing
  • US12288786B2 patent drawing
  • US12288786B2 patent drawing

AI summary

A method of manufacturing an IC structure includes configuring each of an n-well and a p-well in a first IC die to have a first portion extending in a first direction and second and third portions extending from the first portion in a second direction perpendicular to the first direction, and forming IC devices including a first pickup structure electrically connected to the n-well and a second pickup structure electrically connected to the p-well. Forming the IC devices includes forming a PMOS transistor in the second or third portion of the n-well and forming an NMOS transistor in the second or third portion of the p-well.