Shared Word Line Driver Across 3D Memory Tiers
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently sharing word line drivers across different tiers, leading to increased complexity and area usage in semiconductor structures.
Innovation Solution
The implementation of a semiconductor structure with multiple three-dimensional memory arrays sharing a word line driver circuit, where each word line in one array is electrically connected to a respective word line in another array, reducing the total area required for word line driver circuits and optimizing the layout by splitting word lines and select lines across multiple dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each three-dimensional memory array has its own dedicated word line driver circuit, then the operation reliability of each array is ensured, but the total area occupied by word line driver circuits increases and device complexity increases
Solution Approach 1:
The patent merges word line driver circuits from multiple three-dimensional memory arrays into a shared resource. Specifically, word line driver circuits from first and second memory arrays are combined to form a third memory array, reducing the total number of driver circuits while maintaining operational reliability through the shared architecture.
Solution Approach 2:
The shared word line driver circuit is designed to serve multiple memory arrays simultaneously. The driver circuit can selectively drive word lines in different memory arrays through switching mechanisms, enabling one driver circuit to perform the function of multiple dedicated drivers.
2Area of stationary object
If word line driver circuits are shared across different tiers, then the footprint of driver circuits is reduced, but the device complexity increases due to interconnections across dies
Solution Approach 1:
The patent segments the memory device into multiple separate dies, with each die containing a portion of the memory array and associated driver circuits. This segmentation allows for reduced inter-die connectivity requirements compared to full integration, as each die can be independently fabricated and tested before assembly.
Solution Approach 2:
The patent introduces intermediate connection structures such as bonding pads, inter-die vias, and redistribution layers that mediate the connections between shared driver circuits and memory arrays across different dies. These intermediaries simplify the direct interconnections by providing standardized interfaces and routing paths.
3Quantity of substance
If word lines are split across multiple dies, then the page size increases and density improves, but the manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates alignment marks and registration features during the initial fabrication process on each die. These preliminary actions enable precise alignment during subsequent die stacking or bonding processes, ensuring that word lines spanning multiple dies are correctly positioned relative to each other.
Solution Approach 2:
The patent uses identical or replicated structural patterns across multiple dies for the memory arrays and driver circuits. This copying approach ensures that when dies are stacked or connected, the corresponding structures align naturally, reducing the precision requirements for inter-die connections.
Data Source
AI summary
A semiconductor structure includes a peripheral circuit, a first three-dimensional memory array overlying the peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, and a second three-dimensional memory array overlying the first three-dimensional memory array and including a second alternating stack of second insulating layers and second electrically conductive layers containing second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack. The peripheral circuit includes a first word line driver circuit having first word line driver output nodes electrically connected to at least some of the first word lines and at least some of the second word lines, and each first word line is electrically connected to a respective second word line.