Shared Word Line Flash Memory Circuits
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Solution Overview
Problem
The challenge in flash memory arrays is to increase storage density while minimizing the silicon substrate area, as peripheral circuits like word line decoder and driver circuits are not easily scaled down and occupy a large area due to the need for thick dielectric layers and large device sizes.
Innovation Solution
The use of sidewall spacers to pattern a masking layer and form narrow word lines that are self-aligned to floating gates, allowing two word lines to share decoder and driver circuits, reducing the number of these circuits by half and creating space savings, along with the formation of select lines and contact pads using the same process steps, and the implementation of shield plates for separate erasability of blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional word line structures are used, then each word line requires separate decoder and driver circuits, but this occupies large silicon substrate area
Solution Approach 1:
The patent merges adjacent word lines into shared structures, allowing multiple word lines to共用 the same decoder and driver circuits. This reduces the total number of peripheral circuits while maintaining individual word line functionality through selective activation mechanisms.
Solution Approach 2:
The patent creates universal decoder and driver circuits that can serve multiple word lines simultaneously. These circuits are designed to handle multiple word line signals through multiplexing and selective activation, making them multi-functional rather than dedicated to single word lines.
2Reliability
If thick dielectric layers are used for word line structures, then device reliability is improved, but the area occupied by peripheral circuits increases
Solution Approach 1:
By merging word line structures and sharing peripheral circuits, the patent reduces the total area required for peripheral components while maintaining the necessary thick dielectric layers for reliability in the shared structures.
Solution Approach 2:
The patent optimizes the vertical stacking and spatial arrangement of thick dielectric layers in shared word line structures, allowing reliable device operation in a compact footprint by efficiently utilizing the vertical dimension.
3Manufacturing precision
If more decoder and driver circuits are provided, then word line control precision is improved, but storage density decreases
Solution Approach 1:
The patent combines multiple word line control functions into shared decoder and driver circuits, reducing the area available for memory cells while maintaining control precision through sophisticated circuit design that can selectively activate specific word lines within the shared structure.
Solution Approach 2:
The shared decoder and driver circuits are designed as universal components capable of controlling multiple word lines with the same level of precision as dedicated circuits would provide, through multiplexing and selective signal routing mechanisms.
Data Source
AI summary
Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used. The resulting circuits have word lines linked together so that peripheral circuits are shared. Separate erase blocks are established by shield plates.