Shared-Wordline Memory Programming Across QLC and Lower-Density Cells
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Solution Overview
Problem
Existing memory systems require additional hardware and programming logic to enable concurrent writing across different memory types, leading to inefficiencies in performance and bandwidth utilization.
Innovation Solution
Concurrently program less-densely-programmed and more-densely-programmed memory cells by mapping their logical states to corresponding threshold voltage ranges without additional hardware, allowing simultaneous programming across memory types on shared wordlines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If additional hardware and programming logic are added to enable concurrent writing across different memory types, then writing performance and bandwidth utilization are improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a single programming circuit that can handle both less-densely-programmed and more-densely-programmed memory types without requiring separate dedicated hardware for each memory type. The same circuit is configured dynamically based on the target memory density, eliminating the need for additional hardware components while maintaining concurrent writing capability across different memory types.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting programming parameters such as pulse width, voltage levels, and programming strength based on the target memory density. This allows the same hardware circuit to adapt its behavior for different memory types (e.g., SLC, MLC, TLC, QLC) without requiring additional hardware, thereby improving writing performance while avoiding increased device complexity.
2Productivity
If additional hardware is added to support concurrent writing across memory types, then bandwidth efficiency is improved, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent implements a universal programming circuit that serves multiple memory density types, eliminating the need for separate hardware components for each memory type. This reduces manufacturing complexity and cost while enabling concurrent writing operations that improve bandwidth efficiency across SLC, MLC, TLC, and QLC memory types.
Solution Approach 2:
The patent merges the programming functionality for different memory density types into a single integrated circuit. By combining what would traditionally require separate hardware paths into one unified circuit with configurable parameters, the patent reduces manufacturing cost and device complexity while maintaining high bandwidth efficiency through concurrent writing operations.
3Manufacturing precision
If separate programming operations are used for different memory types, then programming precision is maintained, but writing latency increases
Solution Approach 1:
The patent enables continuous concurrent writing operations across different memory types by using a single programming circuit that can switch between memory density types without interruption. This eliminates the need for sequential programming operations, reducing writing latency while maintaining programming precision through dynamic parameter adjustment for each memory type.
Solution Approach 2:
The patent introduces dynamic parameter adjustment capabilities that allow the programming circuit to adapt its behavior in real-time based on the target memory density. This dynamic configuration enables the same circuit to maintain optimal programming precision for different memory types (SLC, MLC, TLC, QLC) while performing concurrent writing operations, thereby reducing writing latency without sacrificing programming accuracy.
Data Source
AI summary
A memory device of a first array of memory cells configured as quad-level cell (QLC) memory or penta-level cell (PLC) memory and including one or more first planes. A second array of memory cells configured as second memory that is less-densely programmed than the first array, the second array including one or more second planes. Control logic receives a first command to program a first set of memory cells of the first array with a first logical state and a second command to program a second set of memory cells of the second array with a second logical state corresponding in threshold voltage range to the first logical state. The first and second sets of memory cells are associated with a shared wordline. The control logic causes the first and second sets of memory cells to be concurrently programmed with a threshold voltage distribution corresponding to the first logical state.