Shared Wrapper Cell Reduces IC Test Area
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity of integrated circuits requires efficient testing procedures, but existing wrapper architectures are area-consuming and complicate design due to the need for multiple wrapper cells per core pin, especially in hierarchical integrated circuits.
Innovation Solution
Implementing a shared wrapper cell system where a group of core pins within a single clock domain share a single wrapper cell, reducing the number of wrapper cells and area usage while maintaining testability by selecting mutually independent pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If one or two wrapper cells are allocated per core pin to enable at-speed testing, then test capability is improved, but area consumption and design complexity increase significantly
Solution Approach 1:
Multiple wrapper cells are merged into a single shared wrapper cell that serves multiple core pins simultaneously. The shared wrapper cell uses multiplexers to dynamically connect to different core pins based on test requirements, reducing the total number of wrapper cells from N (one per pin) to 1 (shared by all pins), thereby significantly reducing area consumption while maintaining test capability.
Solution Approach 2:
The shared wrapper cell is designed to perform multiple functions by dynamically connecting to different core pins through multiplexers. A single wrapper cell structure is made universal to handle input and output operations for multiple core pins, eliminating the need for dedicated wrapper cells for each pin and reducing overall wrapper area.
2Reliability
If one or two wrapper cells are allocated per core pin to enable at-speed testing, then test capability is improved, but design complexity increases
Solution Approach 1:
Multiple wrapper cells are merged into a single shared wrapper cell that serves multiple core pins simultaneously. The shared wrapper cell uses multiplexers to dynamically connect to different core pins based on test requirements, reducing the total number of wrapper cells from N (one per pin) to 1 (shared by all pins), thereby significantly reducing area consumption while maintaining test capability.
Solution Approach 2:
The shared wrapper cell is designed to perform multiple functions by dynamically connecting to different core pins through multiplexers. A single wrapper cell structure is made universal to handle input and output operations for multiple core pins, eliminating the need for dedicated wrapper cells for each pin and reducing overall wrapper area.
3Area of stationary object
If wrapper cells are shared among multiple core pins, then area consumption is reduced, but testability may be compromised
Solution Approach 1:
The shared wrapper cell employs dynamic switching mechanisms using multiplexers that can reconfigure connections between the shared wrapper cell and different core pins based on test requirements. This dynamic reconfiguration ensures that testability is maintained by allowing full access to individual core pins when needed, while area is reduced through sharing during non-critical operations.
Data Source
AI summary
A device that includes a core and a wrapper. The wrapper includes at least one shared wrapper cell that is shared by a group of core pins that belong to a single clock domain. A method for designing a wrapper. The method includes receiving design information representative of a design of a core, locating a group of mutually independent core pins that belong to a single clock domain; and designing a shared wrapped cell that is shared by the group of core pins.