Shared Write Bit Line for Dual Phase Cache Status Bits
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Solution Overview
Problem
Existing cache systems employing the write-back approach require additional resources and increased power consumption due to the implementation of dual phase writes for status bits, which complicates the design and operation of integrated circuits.
Innovation Solution
Implementing a dual phase write mechanism using a single pair of write bit lines for status bit cells, reducing the size of the write bit line column and power consumption by simplifying the circuitry and eliminating the need for additional write bit lines and drivers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dual phase writes are implemented for status bit cells using separate write bit lines, then cache operation efficiency is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent merges the write bit lines for status bit cells into a single shared write bit line that serves multiple cache lines. Instead of having separate write bit lines for each cache line's status bits, the invention combines these resources so that one write bit line column serves multiple status bit cells across different cache lines, thereby reducing device complexity while maintaining dual phase write capability
Solution Approach 2:
The shared write bit line is designed to perform multiple functions: it writes status bits for multiple different cache lines during different phases of the write operation. The write bit line serves as a universal resource that can be dynamically allocated to different status bit cells based on which cache line is being accessed, eliminating the need for dedicated write bit lines for each cache line
2Productivity
If dual phase writes are implemented for status bit cells using separate write bit lines, then cache operation efficiency is improved, but power consumption increases
Solution Approach 1:
By merging multiple write bit lines into a single shared write bit line for status bit cells, the patent reduces the total number of active conductors in the circuit. This consolidation directly reduces dynamic power consumption associated with charging and discharging bit line capacitance during write operations, while the dual phase write mechanism is preserved through careful timing and control of the shared line
3Reliability
If additional write bit lines and drivers are implemented for status bits, then status bit writing capability is improved, but the size of write bit line column increases
Solution Approach 1:
The patent combines multiple write bit lines that would traditionally be required for writing status bits into a single shared write bit line column. This merging approach maintains the full writing capability for status bits across all cache lines by using time-multiplexed access, while significantly reducing the horizontal space required for the write bit line column in the memory array
4Reliability
If additional write bit lines and drivers are implemented for status bits, then status bit writing capability is improved, but device complexity increases
Solution Approach 1:
The invention merges the driver circuitry for multiple write bit lines into a single driver that controls the shared write bit line. This consolidation reduces the number of driver circuits required, simplifying the overall device architecture while maintaining the ability to write status bits reliably to multiple cache lines through phased write operations controlled by word line timing
Data Source
AI summary
A memory includes at least one write bit line and a plurality of memory cells. The at least one write bit line is configured to carry a write bit signal. The plurality of memory cells are arranged in a column and are configured to be selectively coupled to the at least one write bit line. The plurality of memory cells are configured to be selectively read or written in a first phase of a cycle and selectively read or written in a second phase of the cycle using the at least one write bit line.