Sharing Interrupt Vectors in Multi-Processor Systems
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Solution Overview
Problem
In multi-processor computer systems, existing methods for managing interrupts using message-signaled interrupts (MSI) do not scale well, especially when there are limited interrupt vectors available, such as in x86 architecture, leading to inefficiencies in handling interrupts for multiple device components.
Innovation Solution
The method involves assigning the same interrupt vector to multiple device components, allowing for interrupt vector sharing by programming interrupt mapping tables and using separate or shared interrupt descriptor tables to direct interrupts to appropriate processors, enabling efficient processing across multiple processors or virtual processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If message-signaled interrupts (MSI) are used in multi-processor systems, then interrupt handling capability is improved, but scalability is limited due to limited interrupt vectors
Solution Approach 1:
The patent combines multiple device components to share a single interrupt vector. Instead of allocating separate interrupt vectors to each device component, the system merges their interrupt handling by having multiple components share the same interrupt vector, thereby conserving limited interrupt vector resources while maintaining interrupt handling capability across multiple devices.
Solution Approach 2:
The patent makes interrupt vectors universal by enabling a single interrupt vector to serve multiple device components. The interrupt handling mechanism is designed to be multi-functional, where one interrupt vector can trigger interrupt service routines that handle events from different device components, thus increasing the versatility and scalability of the interrupt system.
2Measurement precision
If separate interrupt vectors are allocated to each device component, then interrupt processing accuracy is improved, but interrupt vector exhaustion occurs
Solution Approach 1:
The patent merges the interrupt vector allocation for multiple device components into a shared resource. Instead of providing dedicated interrupt vectors to each component (which would exhaust the limited vector supply), the system combines the interrupt handling of multiple components under shared interrupt vectors, thereby preserving interrupt vector availability while maintaining accurate interrupt processing through component identification within the shared handler.
3Adaptability or versatility
If interrupt vectors are shared among multiple device components, then scalability is improved, but interrupt management complexity increases
Solution Approach 1:
The patent introduces an intermediary mechanism (such as an interrupt controller or management software layer) that mediates between multiple device components and the shared interrupt vectors. This intermediary handles the complexity of routing and managing interrupts from multiple sources through shared vectors, thereby enabling scalability while abstracting away the management complexity from the device components themselves.
Solution Approach 2:
The patent implements feedback mechanisms in the interrupt management system, where interrupt service routines can identify the source device component and provide feedback for proper routing and handling. This feedback loop enables the system to manage shared interrupt vectors effectively, maintaining scalability while controlling complexity through intelligent routing decisions based on interrupt source identification.
Data Source
AI summary
An example method of sharing message-signaled interrupt vectors in multi-processor computer systems comprises: associating an interrupt vector with a first device component, by creating a first interrupt mapping entry of an interrupt mapping table, wherein the first interrupt mapping entry references a first processor and the interrupt vector; associating the interrupt vector with a second device component, by creating a second interrupt mapping entry of the interrupt mapping table, wherein the second interrupt mapping entry references a second processor and the interrupt vector; and creating, in an interrupt descriptor table (IDT) associated with the first processor and the second processor, an interrupt descriptor for the interrupt vector.


