Sheet-Channel Gate Structure for Dense 3D Transistor Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in scaling integration density and suppressing short channel effects while maintaining effective current control, particularly in multi-gate transistors with three-dimensional channels.
Innovation Solution
The semiconductor device incorporates a unique structure with a lower pattern and sheet patterns, featuring a gate structure surrounded by a gate electrode and insulating film, a gate capping pattern, a gate etching stop pattern, and a gate spacer, along with source/drain patterns and contacts, which enhance the scalability and current control capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-gate transistor with three-dimensional channel is used, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The active pattern is segmented into multiple sheet patterns (first sheet pattern, second sheet pattern, etc.) spaced apart in the second direction, with gate structures formed between each sheet pattern. This segmentation enables the multi-gate transistor to achieve three-dimensional channel control while maintaining manufacturability through standardized repeating units.
Solution Approach 2:
The invention transitions from planar gate structures to three-dimensional gate structures that wrap around sheet patterns in multiple directions. The gate electrode and gate insulating film surround each sheet pattern, creating a multi-gate configuration that controls the channel from multiple angles, thereby achieving better current control and scaling in the third dimension.
2Reliability
If gate length is increased to improve current control, then current control capability is improved, but device area increases
Solution Approach 1:
Instead of increasing gate length in the first direction, the invention uses multi-gate structures that control the channel from multiple directions (surrounding the sheet patterns). This three-dimensional gate configuration provides superior current control without requiring longer gate lengths, thereby maintaining compact device area while improving reliability.
3Ease of manufacture
If conventional planar transistor structure is used, then manufacturing is simpler, but short channel effect suppression is insufficient
Solution Approach 1:
The active pattern is divided into multiple sheet patterns with gate structures formed between them. This segmentation creates multiple gate-controlled regions that collectively suppress short channel effects more effectively than a single planar gate, while still using standard manufacturing processes for forming the segmented structures.
Solution Approach 2:
The gate structure transitions from a two-dimensional planar configuration to a three-dimensional configuration that surrounds the sheet patterns. This multi-dimensional gate control provides better electrostatic control over the channel, effectively suppressing short channel effects while maintaining compatibility with existing manufacturing techniques.
Data Source
AI summary
A semiconductor device includes an active pattern with a lower pattern and sheet patterns spaced apart from the lower pattern, a gate structure on the lower pattern and having a gate electrode and a gate insulating film that surround each of the sheet patterns, a gate capping pattern on the gate structure, a gate etching stop pattern between the gate capping pattern and the gate structure, a gate spacer along a sidewall of the gate capping pattern, a source/drain pattern on the gate structure, a gate contact through the gate capping pattern and connected to the gate electrode, upper surfaces of the gate contact and gate spacer being coplanar, and a source/drain contact on the source/drain pattern and connected to the source/drain pattern.