Shield Electrode Trench MOSFET for Low COSS and RdsOn
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Solution Overview
Problem
Medium and high voltage trench MOSFET devices face challenges in achieving low small-signal output capacitance (COSS) and on-resistance (Rdson) while maintaining desired breakdown voltage (BVDSS) and ruggedness, with existing techniques either increasing Rdson or requiring expensive and unreliable ion implantation equipment.
Innovation Solution
The implementation of a semiconductor device structure with a multi-region semiconductor layer having a charge balance region with a higher dopant concentration than a junction blocking region, combined with a trench structure and doped regions, reduces trench depth and electric field build-up, enhancing COSS and BVDSS performance while maintaining low Rdson and improving UIS ruggedness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If trench depth is increased to maintain BVDSS, then breakdown voltage is improved, but small-signal output capacitance (COSS) increases
Solution Approach 1:
The patent segments the semiconductor structure into multiple doped regions with different concentrations (first doped region, second doped region, third doped region) at different depths. This segmentation allows the electric field to be distributed and controlled across regions, enabling reduced trench depth while maintaining breakdown voltage and reducing COSS simultaneously.
Solution Approach 2:
The patent applies local quality by creating regions with different dopant concentrations at specific locations. The first doped region has a first concentration, the second has a second concentration, and the third has a third concentration, with each region optimized for its specific function in controlling electric field distribution and reducing capacitance.
2Weight of moving object
If thick shield electrode liner oxide and thick bottom oxide are used to reduce COSS, then small-signal output capacitance is improved, but on-resistance (Rdson) increases and process yield issues occur
Solution Approach 1:
The patent changes the parameter of dopant concentration across different regions and depths. By optimizing the concentration gradients in the first, second, and third doped regions, the patent achieves low COSS without requiring thick oxides, thereby maintaining low Rdson and avoiding process yield issues.
3Weight of moving object
If high resistive drift region is used to reduce COSS, then small-signal output capacitance is improved, but on-resistance (Rdson) increases
Solution Approach 1:
The patent applies local quality by creating spatially varying dopant concentrations in the drift region. Instead of a uniform high-resistive drift region, the patent implements multiple doped regions with different concentrations at different depths, achieving low COSS while maintaining low Rdson through optimized local electrical properties.
4Weight of moving object
If high energy ion implant is used to place dopant deep into drift region, then COSS is reduced, but expensive equipment is required and process repeatability and yield issues occur
Solution Approach 1:
The patent segments the doping process into multiple regions with different concentrations that can be formed using standard ion implantation equipment. By dividing the dopant placement into first, second, and third doped regions with different concentrations and depths, the patent achieves deep dopant placement without requiring expensive high-energy ion implantation equipment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces COSS, improves switching characteristics, maintains BVDSS, and enhances device ruggedness without the need for expensive equipment, improving process repeatability and yield.
Implementation Method 1
reduces trench depth and electric field build-up, enhancing COSS and BVDSS performance
Implementation Method 2
a second semiconductor layer having a first conductivity type and a second dopant concentration
Data Source
AI summary
A semiconductor device includes a semiconductor region with a charge balance region on a junction blocking region, the junction blocking region having a lower doping concentration. The junction blocking region extends between a pair of trench structures in cross-sectional view. The trench structures are provided in the semiconductor region and include at least one insulated electrode. In some embodiments, the semiconductor device further includes a first doped region disposed between the pair of trench structures. The semiconductor device may further include one or more features configured to improve operating performance. The features include a localized doped region adjoining a lower surface of a first doped region and spaced apart from the trench structure, a notch disposed proximate to the lower surface of the first doped region, and/or the at least one insulated electrode configured to have a wide portion adjoining a narrow portion.