Shield Gate Trench Power Device Dielectric Uniformity
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Solution Overview
Problem
Existing shield gate trench power devices face limitations in increasing breakdown voltage and reducing on-resistance due to non-uniform thickness of the shield dielectric layer, which also affects gate-source capacitance.
Innovation Solution
A shield gate trench power device with a gate structure featuring a stacked thermal oxide and CVD dielectric layer for the shield dielectric layer, ensuring uniform thickness and increased breakdown voltage, along with anisotropic etching to define the top trench and control inter-polysilicon dielectric layer width, reducing gate-source capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the thickness of the thermal oxide layer of the shield dielectric layer is increased to improve breakdown voltage, then the breakdown voltage should be improved, but the thermal oxidation process cannot increase the thickness further due to process limitations and non-uniform thickness distribution
Solution Approach 1:
The shield dielectric layer is segmented into multiple sub-layers: a first dielectric layer (thermal oxide) and a second dielectric layer (CVD oxide). This segmentation allows each layer to contribute differently to the overall function - the thermal oxide layer provides good interface quality while the CVD layer adds thickness uniformly, resolving the contradiction between achieving high breakdown voltage and maintaining thickness uniformity.
Solution Approach 2:
The shield dielectric layer uses a composite structure combining thermal oxide and CVD oxide materials. The thermal oxide layer (3000-7500 Å) provides excellent interface properties with the epitaxial layer, while the CVD oxide layer (2500-7000 Å) deposited on top adds significant thickness with superior uniformity control, achieving both high breakdown voltage and uniform thickness distribution.
2Strength
If the doping concentration of the epitaxial layer is reduced to improve breakdown voltage, then the breakdown voltage is improved, but the on-resistance of the device increases
Solution Approach 1:
The shield dielectric function is segmented between thermal oxide and CVD oxide layers, allowing the epitaxial layer doping concentration to be optimized for low on-resistance without being constrained by breakdown voltage requirements. The CVD oxide layer specifically addresses the breakdown voltage needs, freeing the epitaxial layer doping from this constraint.
3Ease of manufacture
If isotropic etching is used to form the top trench, then the etching process is simple, but the etching rates of different dielectric layers are inconsistent causing non-uniform top trench depth
Solution Approach 1:
The etching process transitions from isotropic to anisotropic specifically for forming the top trench. This localized change in etching methodology ensures that the top trench achieves uniform depth by etching vertically through the dielectric layers at controlled rates, while the rest of the fabrication process maintains simplicity. The anisotropic etching directionality compensates for the different etching rates of thermal oxide and CVD oxide layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances breakdown voltage, reduces on-resistance, and decreases gate-source capacitance while maintaining process cost efficiency by ensuring uniformity and accurate control of the shield dielectric layer thickness.
Implementation Method 1
A gate oxide layer 105 is formed on a first side surface of the top trench, i.e., an exposed side surface of the gate trench 102. The gate oxide layer 105 is generally formed by means of a thermal oxidation process
Implementation Method 2
the shield dielectric layer is formed by stacking a thermal oxide layer and a CVD dielectric layer
Implementation Method 3
anisotropic etching to define the top trench and control inter-polysilicon dielectric layer width
Data Source
AI summary
A shield gate trench power device, wherein a shield dielectric layer is formed by stacking a thermal oxide layer and a CVD dielectric layer on the inner side surface of a gate trench; a gap region formed by means of filling with the shield dielectric layer is filled with source polysilicon; a top trench is formed on two sides of the source polysilicon by etching a portion of the shield dielectric layer close to the side surface of the gate trench, and the entire top trench is located in the thermal oxide layer; the top trench is filled with a polysilicon gate. A method for manufacturing a shield gate trench power device. The uniformity of the thickness of the shield dielectric layer on the sidewall and bottom of the gate trench can be improved.