Shield Line Between Internal Layer and I/O Lines
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Solution Overview
Problem
The reduction in parasitic capacitance and shortening of distances between lines in semiconductor apparatuses lead to decreased noise immunity, causing soft errors from cosmic radiation and signal interference, which existing technologies fail to adequately address.
Innovation Solution
A semiconductor apparatus is designed with a shield line placed between the internal layer and the input/output line layer to cover the internal cell line and power supply line, effectively blocking noise and preventing interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the manufacturing process is moved to finer design rules to increase integration density, then productivity and area utilization are improved, but noise immunity deteriorates due to reduced parasitic capacitance and shorter line distances
Solution Approach 1:
A shield line is introduced as an intermediary element between the bit line and the internal cell line/cross-coupling node. This shield line acts as a mediator that blocks electromagnetic coupling and prevents noise transmission from the voltage-varying internal lines to the sensitive bit line, thereby resolving the noise immunity problem caused by finer design rules
Solution Approach 2:
The harmful electromagnetic interference is extracted and isolated by placing the shield line between the noise source (internal cell line) and the victim line (bit line). The shield line captures and contains the noise field, preventing it from affecting adjacent signal lines and thus maintaining noise immunity at finer process nodes
2Reliability
If additional capacitors are added to increase node capacitance for soft error immunity, then reliability against soft errors is improved, but device complexity and area increase
Solution Approach 1:
The shield line serves multiple functions: it provides electromagnetic shielding to prevent noise coupling, acts as a ground reference for stability, and can be integrated with existing ground structures. This multi-functionality allows the system to achieve noise immunity without adding separate dedicated shielding structures, thus avoiding increased device complexity
3Reliability
If additional capacitors are placed above the SRAM cell to improve soft error immunity, then reliability is improved, but chip area increases
Solution Approach 1:
The shielding function is implemented in the vertical dimension by placing the shield line in an intermediate layer between the bit line layer and the internal cell line layer. This three-dimensional arrangement provides effective noise blocking without requiring additional lateral area, thus maintaining compact chip layout while achieving the shielding function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances signal reliability by blocking voltage variations, thereby improving noise immunity and reducing signal propagation errors.
Implementation Method 1
a shield line which is placed between the internal layer and the input/output line layer so as to cover the internal cell line and the first power supply line... The shield line thereby blocks noises due to voltage variation occurring in the internal cell line or the first power supply line
Data Source
AI summary
A semiconductor apparatus includes an internal layer where a first power supply line to provide a first power supply to transistors in a layout cell and an internal cell line to connect transistors in the layout cell are placed, an input/output line connected with an input/output terminal of the layout cell is placed, and a shield line which is placed between the internal layer and the input/output line so as to cover the internal layer and the first power supply line.