Shield Lines for Program Verify in Multi-Level Cell Memory
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Solution Overview
Problem
The increasing number of levels in multi-level cell (MLC) memory devices leads to a significant increase in programming time due to the need for multiple sense operations during program verify operations, which can degrade the efficiency and accuracy of threshold voltage sensing.
Innovation Solution
The implementation of a method that utilizes capacitive coupling between data lines and shield lines or a shield plate to reduce the sensed memory cell threshold voltage error, by charging and discharging these components during the program verify operation to suppress errors and maintain accurate sensing across multiple levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple sense operations are performed during program verify operations in MLC memory devices, then the accuracy of threshold voltage sensing is improved, but the programming time increases significantly
Solution Approach 1:
The patent applies preliminary action by performing a first sense operation before the second sense operation during program verify. The first sense operation senses a first threshold voltage level, and the second sense operation senses a second threshold voltage level. By structuring the sense operations in a specific sequence with preliminary action, the patent reduces the overall programming time while maintaining accurate threshold voltage sensing across multiple levels.
2Measurement precision
If multiple sense operations are performed during program verify operations, then the accuracy of threshold voltage sensing is improved, but the efficiency of programming deteriorates
Solution Approach 1:
The patent structures the sense operations with preliminary action where the first sense operation is performed before the second sense operation. This sequential arrangement with preliminary sensing allows the memory device to maintain accurate threshold voltage detection while improving programming efficiency by optimizing the order and timing of sense operations.
Solution Approach 2:
The patent maintains continuity of useful action by performing sense operations continuously during the program verify process without unnecessary interruptions. The first and second sense operations are conducted in sequence, ensuring that the useful action of threshold voltage sensing continues throughout the programming process, thereby maintaining high programming efficiency.
3Quantity of substance
If the number of levels in MLC memory devices is increased, then the storage capacity is improved, but the programming time increases due to multiple sense operations
Solution Approach 1:
The patent applies preliminary action by implementing a structured sequence of sense operations where the first sense operation precedes the second sense operation. This approach enables MLC memory devices with increased levels (higher storage capacity) to maintain reasonable programming times by optimizing the sense operation sequence rather than performing all sense operations in a naive manner.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall programming time and improves the accuracy of threshold voltage sensing in MLC memory devices by minimizing errors caused by capacitive coupling, allowing for more efficient programming across multiple levels.
Implementation Method 1
The implementation of a method that utilizes capacitive coupling between data lines and shield lines or a shield plate to reduce the sensed memory cell threshold voltage error
Data Source
AI summary
Memory devices might include an array of memory cells, a plurality of access lines connected to the array of memory cells, a plurality of data lines connected to the array of memory cells, a plurality of shield lines, and control logic. The plurality of shield lines might be interleaved with the plurality of data lines. The control logic might be configured to implement a program verify operation of respective memory cells of the array of memory cells connected to a selected access line including charging the plurality of shield lines to a first voltage level, discharging the plurality of shield lines to a voltage level less than the first voltage level, and sensing a voltage level on each data line to determine whether each respective memory cell coupled to the selected access line has been programmed to a target level for the respective memory cell.