Shield Polysilicon Trench MOSFET Inter-Poly Oxide Control
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Solution Overview
Problem
In semiconductor devices, particularly split-gate trench MOSFETs, the reduction of gate-to-drain capacitance (Cgd) and suppression of gate leakage current are limited due to the challenges in controlling the thickness and quality of inter-poly oxides, which are affected by the limited aspect ratio of trenches during the manufacturing process.
Innovation Solution
A method involving a two-step etching process on shield polysilicon and a two-stage removal process on the isolation oxide layer is performed to mitigate the recess of isolation oxides, allowing for better control of the inter-poly oxide layer deposition without voids, thereby enhancing the thickness and quality control of the inter-layer oxide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If backfill oxides are used as inter-layer oxides during the manufacturing process, then the manufacturing process can be completed, but the thickness and quality of inter-poly oxides cannot be controlled properly resulting in high gate-to-source leakage current
Solution Approach 1:
The patent segments the oxide formation process into two distinct stages: first forming an isolation oxide layer during trench fabrication, then forming the inter-poly oxide layer separately in a subsequent deposition process. This segmentation allows each oxide layer to be optimized independently, with the inter-poly oxide layer being deposited conformally on the isolation oxide layer to achieve precise thickness and quality control without compromising the manufacturing process.
2Device complexity
If conventional trench structures are used, then the device structure is simple, but the ability to reduce gate-to-drain capacitance is limited
Solution Approach 1:
The patent introduces an intermediary isolation oxide layer that extends laterally beyond the trench walls and serves as a mediator between the shield polysilicon and the inter-poly oxide layer. This intermediary structure enables better control over the inter-poly oxide deposition process and enhances the shield gate's ability to reduce gate-to-drain capacitance while maintaining overall structural simplicity.
3Device complexity
If the inter-poly oxide layer is formed without proper isolation oxide layer preparation, then the process is simpler, but voids are formed in the inter-poly oxide layer affecting device performance
Solution Approach 1:
The patent performs preliminary action by forming the isolation oxide layer with lateral extension beyond the trench walls before depositing the inter-poly oxide layer. This preliminary preparation creates a proper foundation that prevents void formation during inter-poly oxide deposition, ensuring high-quality layer formation while maintaining process simplicity through the integrated nature of the approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate-to-drain capacitance and suppresses gate leakage current by ensuring a concave top surface of the inter-poly oxide layer, improving the overall performance of the semiconductor device.
Implementation Method 1
performing a first etching process to remove a first portion of the shield polysilicon and expose a portion of the surface of the isolation oxide layer in the trenches
Implementation Method 2
forming an inter-poly oxide layer on the remaining shield polysilicon and the remaining isolation oxide layer
Data Source
AI summary
A method for forming a semiconductor device is provided. A plurality of trenches are formed in the substrate. An isolation oxide layer is formed in the trenches and on the substrate. A shield polysilicon is deposited in the trenches and on the isolation oxide layer on the substrate. A first etching process is performed to remove a first portion of the shield polysilicon. A first removal process is performed to remove a first portion of the isolation oxide layer. A second etching process is performed to remove a second portion of the shield polysilicon. A second removal process is performed to remove a second portion of the isolation oxide layer. An inter-poly oxide layer is formed on the remaining shield polysilicon and the remaining isolation oxide layer, wherein the inter-poly oxide layer has a concave top surface.