Semiconductor Shield Wiring Layout for Congestion-Free Clock Routing
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Solution Overview
Problem
Existing methods for arranging shield wirings in semiconductor circuits face challenges in selecting ideal wiring paths due to the use of already-arranged power supply or ground nets, leading to potential wiring congestion and inefficiencies, particularly affecting clock wirings.
Innovation Solution
A method involving the arrangement of shield wiring candidates with spacing for wiring tracks, followed by the removal of non-contributing candidates and redundant vias, ensuring optimal placement of shield target wirings like clock wirings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a wiring path is searched so that the signal net is adjacent to an already-arranged power supply net or ground net with a predetermined clearance, then the already-arranged power supply net or ground net can be used as a shield net, but an ideal wiring path cannot be selected due to wiring congestion
Solution Approach 1:
The patent applies preliminary action by arranging shield wiring candidates in advance on both sides of signal nets that require shielding, before the actual wiring path determination is performed. This preliminary arrangement ensures that shielding resources are pre-positioned, allowing the wiring path search to proceed without being constrained by the need to route signal nets adjacent to existing power supply or ground nets. The shield wiring candidates are arranged with a predetermined clearance to serve as future shield nets, thus resolving the contradiction between ensuring shielding effectiveness and maintaining wiring path selection freedom.
2Reliability
If shield wiring candidates are arranged densely to maximize shield coverage, then shield coverage ratio is improved, but wiring track space is reduced
Solution Approach 1:
The patent applies local quality by differentiating the treatment of different regions in the wiring layout. Shield wiring candidates are arranged with a specific clearance (e.g., one wiring track spacing) only in regions where signal nets require shielding, while other regions maintain normal wiring density. This localized approach ensures that shield coverage is provided where needed without unnecessarily reducing wiring track space in other areas, thus resolving the contradiction between maximizing shield coverage ratio and preserving wiring track space.
Data Source
AI summary
A wiring method of the semiconductor circuit device includes arranging a plurality of shield wiring candidates such that the plurality of shield wiring candidates adjacent to each other are arranged apart by a space for a wiring track, arranging a shield target wiring on at least one of wiring tracks between the plurality of shield wiring candidates adjacent to each other, and removing a shield wiring candidate which do not contribute as shield wiring to the shield target wiring arranged.