Shielded Bit Line Architecture for Flash Memory Read Speed
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Solution Overview
Problem
Current flash memory devices face performance bottlenecks due to slower programming and reading speeds, which hinder the performance of systems that incorporate them, despite advancements in system performance.
Innovation Solution
The implementation of a complimentary shielded bit line architecture that allows for simultaneous reading of even and odd bit lines during operations, reducing capacitive coupling and noise, and utilizing switching circuitry to connect only necessary bit lines to data caches while shielding others, thereby enhancing read performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional flash memory architecture is used, then manufacturing and operation are simpler, but read performance is limited due to capacitive coupling and noise between bit lines
Solution Approach 1:
The memory array is divided into multiple segments, with each segment containing a subset of bit lines. Switching circuitry selectively connects only the necessary segments to data caches during read operations, isolating unselected bit lines to reduce capacitive coupling and noise while maintaining simpler operation for selected lines
Solution Approach 2:
Switching circuitry acts as an intermediary between bit lines and data caches, selectively connecting only the bit lines that need to be read. This mediator isolates unselected bit lines from the data cache, reducing noise and capacitive coupling effects on the selected bit lines while maintaining standard memory operation for accessed data
2Productivity
If all bit lines are connected to data caches, then all data can be accessed simultaneously, but capacitive coupling and noise between bit lines increase
Solution Approach 1:
Bit lines are divided into multiple segments grouped by physical proximity. The switching circuitry connects only the segments containing the bit lines that need to be read at any given time, rather than connecting all bit lines to all data caches. This segmentation reduces the number of active connections, thereby reducing capacitive coupling and noise while still enabling parallel access to multiple data pages
Solution Approach 2:
Different segments of bit lines are treated differently based on their selection status. Selected bit line segments are connected to data caches with appropriate voltage levels and shielding, while unselected segments are isolated or placed in high-impedance states. This local differentiation reduces noise and capacitive coupling on the selected lines without sacrificing the parallel access capability for the needed data
Data Source
AI summary
Bit lines of a memory segment are read at substantially the same time by coupling a selected memory segment and, at some of the data lines of any intervening segments, to respective data caches. The bit lines of the unselected memory segments that are not used to couple the selected segment to the data caches can be coupled to their respective source lines.