Shielded Clock Channel Layout for Low-Jitter High-Frequency Signals

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Solution Overview

Problem

High-frequency clock signals experience significant jitter due to electrical interference during distribution in synchronous systems, which can disrupt the synchronization of logic operations and lead to errors in data processing.

Innovation Solution

A clock channel is configured with a shielding tunnel that uses multiple metal layers to shield the clock signal from interference, and power signals are transmitted through a shielding tunnel to power clock repeaters, which retransmit the clock signal with increased power, reducing channel-induced jitter.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If clock signals are transmitted at high frequency to achieve fast synchronization, then the speed of operation is improved, but electrical interference increases causing significant jitter

Engineering Contradiction:
Improveclock signal frequencyVSAvoidsignal stability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent introduces shielding tunnels formed by conductive metal layers as intermediary structures between the clock signal channel and surrounding interference sources. These shielding tunnels act as mediators that block electrical interference from adjacent signal channels while allowing the high-frequency clock signal to pass through with minimal disruption, thus maintaining both speed and reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The shielding tunnels are positioned around the clock channel in advance to prevent electrical interference before it can affect the clock signal. By establishing this protective barrier beforehand, the patent preemptively counteracts the harmful electromagnetic effects that would otherwise cause jitter at high frequencies

Inventive Principle:
Principle #9Preliminary anti-action

2Reliability

If shielding structures are added to protect the clock channel from interference, then signal stability is improved, but device complexity increases

Engineering Contradiction:
Improvesignal stabilityVSAvoidshielding structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the metal layers serve multiple functions: they provide both power distribution to clock repeaters and shielding protection for clock channels. By making the shielding structure multi-functional, the patent avoids adding separate dedicated shielding components, thus improving signal stability without proportionally increasing device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the power delivery function and the shielding function into a single integrated structure. The same metal layers that carry power to the clock repeaters also form the shielding tunnels around the clock channels, merging two protective and supportive functions into one unified structure

Inventive Principle:
Principle #5Merging (Combining)

3Use of energy by moving object

If power signals are transmitted through the same structure to power clock repeaters, then energy efficiency is improved, but electrical interference may increase

Engineering Contradiction:
Improvepower delivery efficiencyVSAvoidelectrical interference
Core Design Contradiction:
Use of energy by moving objectVSObject-affected harmful factors

Solution Approach 1:

The patent positions the clock channel inside the shielding tunnel formed by metal layers, with the power signals transmitted through these same layers. The nested configuration allows the clock channel to be protected by the very structure that delivers power, efficiently containing both functions within the same spatial envelope while the shielding prevents power-related interference from reaching the clock signal

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively minimizes clock jitter to less than 40 pico-seconds peak-to-peak per 20 millimeters of clock channel, ensuring a clean and stable clock signal for high-frequency operations, thereby enhancing the reliability of synchronous systems.

Implementation Method 1

a shielding tunnel configured to shield, in at least four directions, the clock channel from other signals

Methodology Applied
Scientific EffectElectromagnetic shielding: Faraday Cage

Data Source

PatentUS7839161B2Low-jitter high-frequency clock channel
Publication Date: 2010.11.23 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US7839161B2 patent drawing
  • US7839161B2 patent drawing
  • US7839161B2 patent drawing

AI summary

According to one general aspect, an apparatus may include a clock channel, a shielding tunnel, and clock repeaters. In various embodiments, the clock channel may be configured to carry the clock signal, and may include a portion of a metal layer of an integrated circuit. In some embodiments, the shielding tunnel may be configured to shield, in at least four directions, the clock channel from other signals, and may include portions of a at least three metal layers of the integrated circuit. The shielding tunnel may be connected to the positive and negative supplies in order to provide the required power for the clock repeaters.