Shielded Connector Layout for Sub-50 Micron Signal Pins

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor technologies advance, the shrinking dimensions of contact points on semiconductor devices pose significant challenges for making reliable, separable electrical connections, particularly at pitches below 50 microns, where conventional techniques become prohibitively difficult and expensive, especially when simultaneous connection to multiple contact pads is required.

Innovation Solution

A separable and reconnectable connector design that incorporates signal pins shielded by ground pins and buried ground vias, which reduces cross-talk and improves signal integrity while maintaining a compact size, allowing for effective electrical connections to semiconductor components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional electrical connector techniques are used, then ease of manufacture is maintained, but manufacturing precision deteriorates at pitches below 50 microns

Engineering Contradiction:
Improvecontact point pitch precisionVSAvoidconnector fabrication difficulty
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent replaces conventional mechanical stamped metal springs with a photolithographically defined trace pattern on a substrate. This substitution enables precise positioning of contact points at sub-50-micron pitches through photolithography processes, which offer superior dimensional control compared to mechanical forming methods. The trace pattern is formed using standard semiconductor fabrication techniques, making high-precision connectors manufacturable at scale.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the fundamental parameter of contact point formation from mechanical deformation (stamped springs) to photolithographic deposition (traces on substrate). This parameter change enables achieving sub-50-micron pitch precision because photolithography can control feature sizes at this scale, whereas mechanical stamping becomes prohibitively difficult and expensive below 50 microns.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If ground pins are added to shield signal pins, then signal integrity is improved, but device complexity increases

Engineering Contradiction:
Improvesignal integrityVSAvoidconnector structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the ground shielding function with the substrate structure itself. The substrate contains both signal traces and ground traces integrated into a single layered structure, with ground traces positioned adjacent to signal traces to provide shielding. This integration eliminates the need for separate ground pin components, reducing device complexity while maintaining signal integrity through effective electromagnetic shielding.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The substrate serves multiple functions simultaneously: it provides mechanical support, defines the array geometry, forms the electrical traces, and provides ground shielding through integrated ground traces. This multi-functionality reduces overall device complexity by consolidating what would otherwise require separate components into a single unified structure.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If connector size is increased to accommodate shielding, then signal integrity is improved, but volume increases

Engineering Contradiction:
Improvesignal integrityVSAvoidconnector volume
Core Design Contradiction:
ReliabilityVSVolume of moving object

Solution Approach 1:

The patent moves the ground shielding function from a lateral arrangement (separate ground pins surrounding signal pins in the plane) to a vertical/planar integration within the substrate layers. Ground traces are positioned in adjacent regions on the same substrate plane and can also extend into different layers, providing shielding without increasing the overall connector footprint. This dimensional reorganization enables effective shielding within a compact volume.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The ground traces are nested within the substrate structure, with signal traces and ground traces co-planar or in adjacent layers. The ground shielding function is nested within the same physical envelope as the signal transmission function, rather than requiring external ground pins that would increase connector volume. This nesting enables compact design with integrated shielding.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The use of buried ground vias provides effective shielding for signal pins, reducing crosstalk and enhancing signal integrity in a compact form factor, enabling reliable connections at smaller pitches without the need for increased connector size or complexity.

Implementation Method 1

A separable and reconnectable connector includes a contact array including signal pins that are shielded by ground pins and by buried ground vias

Methodology Applied
Scientific EffectElectromagnetic shielding: Faraday Cage

Data Source

PatentUS11967782B2Connector including signal pins shielded by buried ground vias
Publication Date: 2024.04.23 NEOCONIX INC
  • US11967782B2 patent drawing
  • US11967782B2 patent drawing
  • US11967782B2 patent drawing

AI summary

A connector for electrically connecting to conductive structures formed on a semiconductor device includes a core including an isolation layer and signal vias and ground vias formed in the isolation layer; a first ground plane formed on a surface of or in the core and electrically connected to the ground vias; a first set of contact elements formed on a first surface of the core and electrically connected to the signal vias to form signal pins; a second set of contact elements formed on the first surface and electrically connected to a subset of the ground vias to form ground pins. The remaining ground vias without contact elements form buried ground vias. The first and second sets of contact elements are arranged on the first surface of the core to surround each signal pin by at least one adjacent ground pin and one or more adjacent buried ground vias.