Shielded Coplanar Line With Rear-Surface Trench
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Solution Overview
Problem
Coplanar waveguides in radio frequency integrated circuits suffer from high attenuation coefficients due to capacitive and resistive coupling with semiconductor substrates, leading to limited transmission performance and increased manufacturing costs when using high-resistivity substrates or complex metallization structures.
Innovation Solution
A method for manufacturing shielded coplanar lines on the rear surface of an integrated circuit involves forming through vias and a coplanar line with a central conductor narrower than the hole it is formed in, using a conductive material to line the hole walls, and filling with an insulating material of low permittivity to reduce substrate interaction and electromagnetic radiation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional coplanar lines are used on semiconductor substrates, then the structure is simple and manufacturing is easy, but the attenuation coefficient is high due to capacitive coupling with the substrate
Solution Approach 1:
An insulating layer is introduced as an intermediary between the coplanar line and the semiconductor substrate. This mediator reduces the capacitive coupling between the conductive tracks and the substrate, thereby lowering the attenuation coefficient while maintaining manufacturing simplicity through standard semiconductor fabrication processes
Solution Approach 2:
The permittivity parameter of the insulating layer is specifically optimized to reduce capacitive coupling. By selecting materials with appropriate dielectric properties and controlling the layer thickness, the attenuation coefficient is reduced without complicating the manufacturing process
2Loss of energy
If high-resistivity substrates are used to reduce resistive loss, then the attenuation coefficient decreases, but the manufacturing cost increases ten times and additional manufacturing steps are required
Solution Approach 1:
Instead of changing the substrate material to high-resistivity types, an insulating layer is used as an intermediary to reduce capacitive coupling. This approach maintains compatibility with standard low-cost silicon substrates while achieving reduced attenuation, avoiding the ten-fold cost increase associated with high-resistivity substrates
Solution Approach 2:
The patent uses a thin insulating layer that can be easily deposited and integrated into standard manufacturing processes, replacing the need for expensive high-resistivity substrates. This inexpensive intermediate layer achieves the desired performance improvement without requiring costly substrate changes
3Loss of energy
If the distance between the coplanar line and substrate is increased to reduce substrate coupling, then the attenuation coefficient decreases, but the total height of the dielectric layer becomes too large for current manufacturing methods
Solution Approach 1:
The permittivity parameter of the insulating layer is optimized to achieve effective electrical isolation at minimal physical thickness. By using materials with appropriate dielectric properties, the patent reduces capacitive coupling without requiring excessive physical distance, keeping the dielectric layer height within manufacturable limits
Solution Approach 2:
The insulating layer provides localized electrical isolation precisely where needed - between the coplanar line and the substrate - without requiring uniform increases in overall dielectric thickness throughout the structure. This targeted approach reduces substrate coupling while maintaining compact dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a low-cost, low-attenuation coplanar waveguide with an attenuation coefficient two times smaller than conventional lines, while maintaining electromagnetic shielding and reducing resistive losses.
Implementation Method 1
coating with a conductive material the walls and the bottom of the first hole and of the second hole
Implementation Method 2
filling the first and second holes with an insulating filling material
Data Source
AI summary
In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.