Shielded Die-to-Pad Contacts for Leadless RF Semiconductor Packages
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Solution Overview
Problem
Conventional flat no-lead semiconductor packages face challenges in design and manufacturing due to limited leadframe finger and tie bar lengths, as well as radio frequency interference issues, making it difficult to achieve high yields and adequate RF shielding.
Innovation Solution
A leadless semiconductor package design featuring a conductive base with apertures for conductive pillars, where the dielectric fill material isolates the pillars and provides RF shielding, allowing for surface mount pads that mitigate finger length and tie bar length limitations and enhance RF interference protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If leadframe fingers and tie bars are made longer to accommodate floorplan dimensions, then device area is increased, but warpage and non-co-planarity occur during solder reflow process
Solution Approach 1:
The patent segments the leadframe structure into multiple independent fingers that are connected through the IC die rather than through long tie bars. Each finger is kept short and rigid, eliminating the warpage issues associated with long tie bars while maintaining the necessary device area through the distributed finger arrangement.
Solution Approach 2:
The patent transitions from a two-dimensional leadframe array connected by tie bars to a three-dimensional structure where vertical conductive pillars extend from the IC die through the package substrate to connect to external pads. This vertical dimension replaces the need for long horizontal tie bars, maintaining electrical connectivity without the warpage problems.
2Manufacturing precision
If leadframe fingers are made shorter to reduce warpage, then co-planarity is improved, but routing capability and device functionality are limited
Solution Approach 1:
The patent uses vertical conductive pillars extending through the package substrate to provide routing capability, replacing the need for long horizontal leadframe fingers. This vertical dimension allows for effective routing and signal transmission while keeping the horizontal leadframe fingers short and rigid for optimal co-planarity.
Solution Approach 2:
The IC die acts as an intermediary structure that provides vertical conductive pathways through conductive pillars. These pillars extend from the die pads through the package substrate to external mounting pads, serving as the intermediary routing path that eliminates the need for long horizontal leadframe fingers while maintaining routing capability.
3Ease of manufacture
If leadframe structure is used for electrical connections, then manufacturing is simplified, but RF interference occurs between adjacent leadframes
Solution Approach 1:
The patent extracts the RF interference problem by removing the adjacent leadframe structures that cause the interference. Instead of using a dense array of leadframe fingers, the design uses isolated vertical conductive pillars that extend from the IC die through the package substrate, eliminating the mutual inductance and capacitive coupling between adjacent leadframes.
Solution Approach 2:
The package substrate with its ground planes and shielding structures serves as an intermediary that isolates the vertical conductive pillars from each other. This intermediary structure provides RF shielding and reduces interference while maintaining the electrical connectivity function, combining manufacturing simplicity with RF performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient manufacturing and effective RF shielding, improving yield and performance by using a conductive base with apertures and dielectric fill material to isolate and shield conductive pillars, facilitating reliable RF signaling and mechanical connection to circuit boards.
Implementation Method 1
a dielectric fill material disposed in the plurality of apertures and insulating the conductive pillars from the conductive base
Implementation Method 2
the dielectric fill material is configured to suppress transmission of signals at the one or more radio frequencies
Data Source
AI summary
A leadless semiconductor package includes a conductive base having a plurality of apertures formed around a perimeter of the conductive base and extending from a first surface to an opposing second surface of the conductive base. The semiconductor package further includes an IC die having a third surface facing the first surface of the conductive base and having a plurality of conductive pillars disposed thereon. Each conductive pillar extends from the third surface to the first surface via a corresponding aperture. A dielectric fill material is disposed in the apertures and insulates the conductive pillars from the conductive material of the conductive base. An opening of an aperture at the second surface, the bottom end of the conductive pillar disposed therein, and the dielectric fill material at the opening of the aperture at the second surface together form a surface mount pad for mounting the semiconductor package to a corresponding pad of a circuit board.