Shielded Display Transistor Layout Against Induced Substrate Charges
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Solution Overview
Problem
Unintentional induced charges generated in the substrate due to signal lines for NMOS and PMOS transistors affect the movement direction and mobility of carriers in the semiconductor channel area of the driving transistor, leading to changes in element characteristics.
Innovation Solution
A display device with a shielding layer overlapping signal lines for NMOS and PMOS transistors, using different materials for the transistors and a shielding layer to prevent induced charges, maintaining element characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If signal lines for NMOS and PMOS transistors are disposed adjacent to each other, then the device can operate with proper transistor control, but induced charges are generated in the substrate affecting driving transistor characteristics
Solution Approach 1:
A shielding layer is introduced as an intermediary component between the signal lines and the substrate. This shielding layer acts as a mediator that blocks the harmful electromagnetic coupling from the signal lines to the substrate, preventing induced charge generation while allowing the signal lines to maintain their control function over the transistors.
Solution Approach 2:
The shielding layer converts the harmful electromagnetic field from the signal lines into a beneficial protective barrier. By positioning the shielding layer to overlap the signal lines, the electromagnetic field is redirected or contained, transforming the potential harm of induced charges into a controlled field that does not affect the substrate or driving transistor characteristics.
2Adaptability or versatility
If different types of transistors (NMOS and PMOS) are disposed on the substrate, then carrier mobility and leakage current characteristics can be adjusted, but element characteristics of the driving transistor change due to induced charges
Solution Approach 1:
The shielding layer serves as a protective intermediary that isolates the driving transistor from the harmful effects of adjacent signal lines. This allows the device to maintain the benefits of having both NMOS and PMOS transistors for adjustable carrier mobility and leakage current characteristics, while the shielding layer ensures the driving transistor's element characteristics remain stable and reliable.
3Reliability
If a shielding layer is added to prevent induced charges, then element characteristics of the driving transistor are stabilized, but device structure becomes more complex
Solution Approach 1:
The shielding layer is designed to serve multiple functions simultaneously: it acts as a shield against induced charges, provides structural support, and can be integrated with existing device layers. By making the shielding layer multi-functional, the patent reduces the need for additional separate components, thereby limiting the increase in device complexity while achieving reliable stabilization of element characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The shielding layer effectively prevents induced charges, stabilizing the element characteristics of the driving transistor.
Implementation Method 1
a shielding layer overlapping the first scan line in a thickness direction
Data Source
AI summary
Provided is a display device comprising a light-emitting element, a driving transistor configured to supply a drive current to the light-emitting element based on a voltage of a gate electrode thereof and having a driving channel including a first material, a first transistor connected to one of first and second electrodes of the driving transistor and having a first channel, a light-emission control line connected to a gate electrode of the first transistor, a second transistor connected to the second electrode of the driving transistor and having a second channel including a second material different from the first material, a first scan line connected to a gate electrode of the second transistor, and a shielding layer overlapping the first scan line.