Shielded Floating Diffusion Metal Lines for CMOS Image Sensors
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Solution Overview
Problem
Typical image sensing pixels experience reduced sensitivity due to increased parasitic capacitances formed by metal lines associated with floating diffusion nodes, which decreases the pixel conversion gain and light sensitivity.
Innovation Solution
The implementation of shielded floating diffusion nodes, where metal lines associated with the floating diffusion node are at least partially surrounded by pixel output lines, utilizing the Miller effect to reduce parasitic capacitances through electrostatic shielding, similar to a Faraday cage arrangement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal lines are added to connect floating diffusion nodes, then electrical connectivity is improved, but parasitic capacitance increases and conversion gain decreases
Solution Approach 1:
The patent applies nesting by placing the floating diffusion node metal lines inside a shield formed by pixel output metal lines. The shield lines are positioned to surround the floating diffusion node lines, creating a nested configuration where the inner lines (floating diffusion) are enclosed by outer lines (shield). This nested arrangement reduces parasitic capacitance between the floating diffusion lines and other metal lines in the pixel, while maintaining necessary electrical connectivity.
2Area of stationary object
If metal lines are positioned close together for compact layout, then area is reduced, but parasitic capacitance increases and sensitivity decreases
Solution Approach 1:
The patent uses nesting to achieve compact layout while controlling parasitic capacitance. The shield lines are integrated into the existing metal line routing, surrounding the floating diffusion lines within the same compact pixel area. This nested configuration allows close positioning of metal lines for area efficiency while the shield geometry controls the parasitic capacitance between adjacent lines.
Solution Approach 2:
The patent converts the potentially harmful effect of close metal line spacing into a benefit by using the same close-spaced lines as electrostatic shields. The pixel output lines, which would normally contribute to parasitic capacitance, are repositioned and configured to act as shields around the floating diffusion lines, transforming the harmful capacitance into a protective shielding effect that reduces overall parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement significantly reduces the overall capacitance of the floating diffusion nodes, enhancing the conversion gain and light sensitivity of the imaging pixels by minimizing parasitic capacitances.
Implementation Method 1
metal lines associated with the floating diffusion node are at least partially surrounded by pixel output lines, utilizing the Miller effect to reduce parasitic capacitances through electrostatic shielding, similar to a Faraday cage arrangement
Implementation Method 2
utilizing the Miller effect to reduce parasitic capacitances through electrostatic shielding
Data Source
AI summary
An imaging system may include imaging pixels. Each imaging pixel may include floating diffusion metal lines associated with a floating diffusion node in that imaging pixel, pixel output metal lines associated with a pixel output, and additional metal lines. The floating diffusion metal lines node may be at least partially surrounded by the pixel output metal lines. Because the floating diffusion metal lines are at least partially surrounded by the pixel output metal lines, the parasitic capacitance between the floating diffusion metal lines and the additional metal lines may be reduced. A source-follower transistor in each imaging pixel may provide a gain between the floating diffusion metal lines and the pixel output metal lines. Due to the Miller effect, the gain induced by the source-follower transistor may reduce the parasitic capacitance between the floating diffusion metal lines and the pixel output metal lines.