Shielded Gate Transistor Layout for Lower Gate-Drain Capacitance
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Solution Overview
Problem
Pseudomorphic high electron mobility transistors (pHEMTs) used in microwave and millimeter wave amplifiers are limited by parasitic impedances, which restrict their maximum gain due to parasitic capacitances, inductances, and resistances.
Innovation Solution
A transistor design featuring a conductive interconnect with shield walls that extend into the dielectric between the gate and drain electrodes, intercepting electric fields and reducing parasitic effects, thereby enhancing gain by coupling source electrodes through a conductive interconnect with shield walls that mitigate electric field interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional pHEMT structure is used, then device simplicity is maintained, but parasitic impedances limit maximum gain
Solution Approach 1:
A conductive interconnect with integrated shield walls is introduced as an intermediary element between the source electrodes. This interconnect serves dual purposes: electrically coupling the source electrodes while simultaneously providing electromagnetic shielding to reduce parasitic effects, thereby improving maximum gain without significantly complicating the manufacturing process
Solution Approach 2:
The conductive interconnect is designed to perform multiple functions simultaneously: it acts as an electrical conductor to couple the source electrodes and as an electromagnetic shield to reduce parasitic capacitance and inductance. This multi-functionality allows the device to achieve higher gain while maintaining relatively simple structure
2Reliability
If shield walls are added to reduce parasitic effects, then maximum gain is improved, but device complexity increases
Solution Approach 1:
The shielding function is merged with the interconnect structure by integrating shield walls directly into the conductive interconnect that couples the source electrodes. This consolidation eliminates the need for separate shielding components, reducing overall device complexity while still achieving the desired reduction in parasitic effects and improvement in maximum gain
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design increases maximum gain by up to 2 dB at 40 GHz and reduces gate-to-drain capacitance, improving the performance of pHEMTs in high-frequency applications.
Implementation Method 1
A conductive interconnect couples the first source electrode and the second source electrode and extends over the dielectric, wherein the conductive interconnect comprises a shield wall that extends from the conductive interconnect into the dielectric between the gate electrode and the drain electrode
Data Source
Figure 1~2
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Figure 5~7
AI summary
A transistor is disclosed having a substrate (12), a device layer (14) disposed over the substrate, a gate electrode (16) disposed over the device layer, and a drain electrode (18) disposed over the substrate and spaced from the gate electrode. A first source electrode (20) is disposed over the substrate opposite the drain electrode and spaced from the gate electrode. A second source electrode (22) is disposed over the substrate spaced from the drain electrode opposite the gate electrode. A dielectric (26) is disposed over the device layer, the gate electrode, and the drain electrode between the first source electrode and the second source electrode. A conductive interconnect (28) couples the first source electrode and the second electrode and extends over the dielectric. The conductive interconnect comprises a shield wall (30) that extends from the conductive interconnect into the dielectric between the gate electrode and the drain electrode with a distal end that is spaced above the device layer.