Shielded Gate FET Self-Aligned Trench Formation
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Solution Overview
Problem
The reduction of cell pitch in vertical trench gate MOSFETs is limited by manufacturing and design constraints, including misalignment tolerances and increased process complexity, which hinders the reduction of on-resistance and requires costly lithography changes.
Innovation Solution
A shielded gate field effect transistor is formed using a self-aligned process with a single mask to create trenches, body, and source regions, achieving a corrugated doping profile that reduces channel length and eliminates the need for heavy body region formation, thereby reducing on-resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If cell pitch is reduced to increase MOSFET density, then on-resistance decreases, but manufacturing precision and alignment tolerances deteriorate
Solution Approach 1:
The patent combines multiple formation steps into a single lithography exposure step. The trenches, body regions, and source regions are all formed simultaneously using one mask pattern, eliminating sequential alignment steps and their associated tolerance accumulation. This merging approach allows higher MOSFET density without sacrificing alignment precision.
Solution Approach 2:
The single mask pattern is designed in advance to define all critical features (trenches, body regions, source regions) before any fabrication steps begin. This preliminary definition of all features in one step establishes precise relative positions upfront, avoiding subsequent alignment operations that would compromise precision at reduced pitch dimensions.
2Manufacturing precision
If conventional multi-step masking is used to form trenches and doped regions, then manufacturing precision can be maintained, but device complexity and process steps increase
Solution Approach 1:
The patent merges the formation of trenches, body regions, and source regions into a single lithography and etching sequence. Instead of using separate masks for each feature, one integrated mask pattern defines all features, reducing the process from multiple discrete steps to a unified process flow with fewer intervention points.
Solution Approach 2:
The single mask pattern serves multiple functions simultaneously: it defines trench locations, body region boundaries, and source region positions. This multi-functional mask design eliminates the need for separate specialized masks for each feature type, simplifying the overall manufacturing process while maintaining precise feature definition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the number of process steps, achieves lower on-resistance, and minimizes misalignment issues, enabling more efficient and cost-effective manufacturing of MOSFETs with improved electrical properties.
Implementation Method 1
a body region of a second conductivity type is formed in the semiconductor region by implanting dopants
Data Source
AI summary
A method for forming a shielded gate field effect transistor includes the following steps. Trenches are formed in a semiconductor region of a first conductivity type. A shield electrode is formed in a bottom portion of each trench, the shield electrode being insulated from the semiconductor region by a shield dielectric. A gate electrode recessed in each trench is formed over the shield electrode, the gate electrode being insulated from the shield electrode. Using a first mask, a body region of a second conductivity type is formed in the semiconductor region by implanting dopants. Using the first mask, source regions of the first conductivity type are formed in the body region by implanting dopants.