Shielded Gate MOSFET Fabrication Using Self-Aligned Contact Scheme

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Solution Overview

Problem

Existing fabrication techniques for shielded gate trench MOSFETs are complex and expensive, requiring multiple masks, which increases production costs and complexity.

Innovation Solution

A self-aligned contact scheme using only four masks to fabricate shielded gate MOSFETs, reducing the number of masks required and improving device characteristics such as breakdown voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing fabrication techniques with 6 or more masks are used, then device performance parameters can be achieved, but fabrication complexity and production cost increase

Engineering Contradiction:
Improvedevice performanceVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple fabrication steps into fewer process stages, using a self-aligned contact scheme that integrates contact formation with the main fabrication flow. This merging of operations reduces the total number of masks from 6 or more to just 4 masks, simplifying the overall fabrication process while maintaining device performance.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The self-aligned contact scheme performs contact alignment preliminarily during the trench formation stage, rather than requiring separate alignment steps later. This preliminary action establishes the contact positions relative to the trenches before subsequent processing, eliminating the need for additional alignment masks and reducing fabrication complexity.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If existing fabrication techniques with 6 or more masks are used, then device performance parameters can be achieved, but production cost increases

Engineering Contradiction:
Improvedevice performanceVSAvoidproduction cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

By merging multiple fabrication operations into a unified self-aligned process using only 4 masks, the patent reduces material consumption (fewer masks), process time, and manufacturing steps. This directly lowers production costs while maintaining the ability to achieve required device performance parameters through the integrated process design.

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If self-aligned contact scheme with 4 masks is used, then fabrication complexity and production cost are reduced, but device characteristics such as breakdown voltage need to be maintained or improved

Engineering Contradiction:
Improvefabrication simplicityVSAvoidbreakdown voltage
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The self-aligned contact scheme preliminarily positions contacts with precise alignment to trench structures during the early fabrication stage. This preliminary alignment ensures optimal electrical characteristics and field distribution, which maintains or improves breakdown voltage performance while using fewer masks and simplifying the overall process.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10680097B2MOSFET device and fabrication
Publication Date: 2020.06.09 ALPHA & OMEGA SEMICONDUCTOR INC
  • US10680097B2 patent drawing
  • US10680097B2 patent drawing
  • US10680097B2 patent drawing

AI summary

A semiconductor device, comprising: a substrate; an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; a gate pickup trench in the substrate; a first conductive region and a second conductive region disposed in the gate pickup trench, the first conductive region and the second conductive region being separated by oxide, wherein at least a portion of the oxide surrounding the first conductive region in the gate pickup trench is thicker than at least a portion of the oxide under the second conductive region; and a body region in the substrate.