Shielded Gate Trench MOSFET Planarized IPO for Lower Igss and Rg
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Solution Overview
Problem
Conventional shielded gate trench (SGT) MOSFETs face issues with high gate-source leakage current (Igss) and gate resistance (Rg) due to non-planarized inter-polysilicon oxide (IPO) formation, which results in increased on-resistance and switching loss.
Innovation Solution
A method involving multiple polysilicon dry etches and field oxide wet etches to form a planarized thermally grown IPO, ensuring the shielded gate electrode is coplanar with the field oxide, reducing the area of IPO and smoothing the gate electrode corners, thereby minimizing Igss and Rg.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single polysilicon dry etch method is used to form the shielded gate electrode, then the manufacturing process is simpler, but the IPO area increases and sharp corners are formed, resulting in high Igss
Solution Approach 1:
The single polysilicon etch process is divided into two separate etching steps: a first polysilicon dry etch to form the shielded gate electrode, and a second polysilicon dry etch to form the gate electrode. This segmentation allows independent optimization of each electrode's geometry, enabling the shielded gate to have a planar top surface that reduces IPO area and eliminates sharp corners, thereby reducing Igss while maintaining manufacturing feasibility
Solution Approach 2:
The first polysilicon dry etch is performed as a preliminary action to form the shielded gate electrode with a controlled top surface height before the second etch. This preliminary formation allows the shielded gate to serve as a template that limits the subsequent gate electrode formation, preventing sharp corners and reducing the IPO area where leakage would occur
2Ease of manufacture
If field oxide is fully removed from upper portions of sidewalls, then the gate electrode can be formed, but the sidewalls are damaged and the structure becomes non-planar, increasing Igss
Solution Approach 1:
The field oxide is partially removed in a first oxide removal step before polysilicon deposition, creating a preliminary structure where field oxide remains on the upper sidewalls. This preliminary retention of field oxide protects the sidewalls during subsequent processing and establishes a planar reference surface for the shielded gate electrode formation
Solution Approach 2:
The field oxide on the upper sidewalls acts as an intermediary protective layer during the second polysilicon dry etch process. It prevents plasma damage to the sidewalls while allowing the gate electrode to be formed with a planar top surface, thereby maintaining both manufacturability and structural precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces specific on-resistance, enhances frequency efficiency, and addresses high Igss and Rg issues by creating a more planarized structure with a reduced IPO area and smoother gate electrode corners.
Implementation Method 1
A field oxide is formed on sidewalls and bottoms of the gate trenches
Implementation Method 2
A gate oxide and an IPO are thermally grown simultaneously on upper portions of sidewalls of the gate trenches and the shielded gate electrodes, respectively
Data Source
AI summary
Shielded gate devices having a planarized thermally grown (PTG) inter-poly oxide (IPO) structure are disclosed. By using a method having double wet etching processes of a field oxide and double dry etching processes of a first doped polysilicon, the PTG IPO structure is achieved to reduce gate-source leakage current Igss and gate resistance Rg. A gate oxide and a PTG IPO are thermally grown simultaneously. The devices further comprise a current spreading region surrounding a lower portion of a gate electrode for on-resistance reduction.