Shielded Gate MOSFET Cell Layout for Voltage Overshoot Suppression
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Solution Overview
Problem
High power semiconductor devices experience voltage spikes and power loss during switching due to parasitic inductors, which are exacerbated by faster switching, and traditional RC snubbers increase component cost and power loss.
Innovation Solution
Implement a fast/slow cell design with shielded gate MOSFETs, using a gate resistor and shield-to-gate connections to adjust the gate RC time constant, allowing for fast switching with minimal power loss and effective voltage overshoot suppression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If traditional RC snubbers are used to suppress voltage overshoots, then voltage overshoot is reduced, but component cost and power loss increase
Solution Approach 1:
The semiconductor device is divided into multiple cells with different switching speeds - fast cells for normal operation and slow cells for voltage overshoot suppression. This segmentation allows the system to achieve voltage protection without the continuous power loss associated with traditional RC snubbers, as only specific cells operate in the slower mode when needed.
Solution Approach 2:
Different regions of the semiconductor device are assigned different characteristics - some cells have faster switching for efficiency while others have slower switching for voltage control. This local differentiation enables voltage overshoot suppression in specific areas without compromising the overall efficiency of the entire device.
2Productivity
If faster switching is used to improve efficiency, then power loss is reduced, but voltage spikes are exacerbated
Solution Approach 1:
The device segments switching operations between fast cells and slow cells. Fast cells handle normal high-speed switching for efficiency, while slow cells are specifically designed to suppress voltage spikes during switching events, thereby resolving the contradiction between switching speed and voltage spike generation.
Solution Approach 2:
The slow cells act as an intermediary mechanism between the fast switching cells and the voltage spikes they generate. By introducing this intermediate layer with different switching characteristics, the system can maintain high overall efficiency while suppressing harmful voltage transients.
3Device complexity
If uniform switching speed is used across all cells, then device complexity is reduced, but voltage overshoot cannot be suppressed effectively
Solution Approach 1:
Rather than using a single uniform cell design, the device segments cells into different types with different switching characteristics. This segmentation increases device complexity slightly but enables effective voltage overshoot suppression, demonstrating that the added complexity is justified by the performance improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively suppresses voltage overshoots while maintaining high efficiency by balancing fast and slow switching cells within a die, reducing power loss and preventing damage to the gate oxide.
Implementation Method 1
using a gate resistor and shield-to-gate connections to adjust the gate RC time constant
Implementation Method 2
High power semiconductor devices experience voltage spikes and power loss during switching due to parasitic inductors
Data Source
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AI summary
Devices and methods are disclosed for facilitating faster switching of silicon-based and silicon carbide-based power transistors suitable for use in electric vehicles. The disclosed techniques can minimize the impact on turn-on and turn-off losses, while reducing gate voltage and drain voltage spikes during device switching. A fast/slow cell design incorporating shielded gate MOSFETs controls gate-to-drain capacitance and gate resistances to optimize suppression of voltage overshoot.